Texas Instruments TUSB9261PVP

Overview

TUSB9261PVP from Texas Instruments is a USB 3.0 to SATA II bridge IC integrating an ARM Cortex-M3 microcontroller, SuperSpeed USB 3.0 PHY, SATA Gen2-compliant AHCI controller, 64 kB ROM, and 80 kB RAM. It supports UASP and BOT protocols for high-throughput mass storage bridging in external HDD/SSD enclosures with 40 MHz crystal clocking and dual 1.1-V/3.3-V power domains.

For engineers reviewing the TUSB9261PVP datasheet, TUSB9261PVP pinout, TUSB9261PVP application, or TUSB9261PVP equivalent, key selection criteria include SATA Gen2 (3 Gbps) link compatibility, UASP protocol support for reduced latency, integrated M3 firmware extensibility via SPI flash, and HTQFP-64 package routing constraints for differential USB/SATA pairs.

Technical Context

The TUSB9261PVP implements a full USB 3.0 device stack with endpoint controller and adaptive equalizer for SS receiver jitter tolerance, alongside an AHCI-compliant SATA host bus adapter supporting Gen1i/Gen1m/Gen2i/Gen2m signaling modes. Its ARM Cortex-M3 subsystem executes boot code from ROM, loads application firmware from external SPI flash, and manages GPIO, UART debug, PWM LED control, and JTAG boundary scan.

Power architecture separates digital core (VDD = 1.1 V) and I/O/analog (VDD33/VDDA33 = 3.3 V) rails with thermal pad grounding (VSS, Pin 65). Clock generation accepts either 40 MHz crystal (XI/XO with 20 pF load) or external oscillator, with FREQSEL[1:0] pins configuring PLL multiplier; spread-spectrum clocking reduces EMI without external components.

Key Specifications

Pinout & Package

Package: HTQFP-64 (7.00 × 7.00 mm), thermally enhanced with exposed VSS pad (Pin 65). Pin functions validated per TI SLLSE67I Rev I datasheet (March 2016).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar USB-to-SATA bridge applications.

Compared with ASMedia ASM1083 and Microchip USB5744, the TUSB9261PVP uniquely integrates USB 3.0 device controller, SATA AHCI host adapter, and programmable Cortex-M3 in a single HTQFP-64 package-enabling complete, self-contained USB-to-SATA bridging without companion ICs or host CPU intervention.

Availability

TUSB9261PVP is available at Aetrix Electronics and suitable for external HDD enclosures, USB 3.0 SSD docking stations, and optical drive adapters requiring stable component supply across industrial temperature ranges and long product lifecycles.

Supply support for TUSB9261PVP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in interface, power management, and microcontroller technologies.

The TUSB9261PVP belongs to TI's USB bridge controller product line, designed specifically to simplify high-speed mass storage connectivity between USB 3.0 hosts and SATA storage devices in consumer and industrial enclosures.

FAQ

What USB protocols does the TUSB9261PVP support?

The TUSB9261PVP supports USB Attached SCSI Protocol (UASP) for low-latency command queuing and USB Mass Storage Class Bulk-Only Transport (BOT) for broad OS compatibility. It implements all 13 error cases defined in the BOT specification and supports USB bootability and HID-class firmware updates. The TUSB9261PVP firmware presents BOT as the primary interface and UASP as the secondary interface, selectable via SET_INTERFACE request.

Does the TUSB9261PVP require an external crystal or oscillator?

Yes-the TUSB9261PVP requires a 40 MHz clock source, which may be either a parallel-resonant crystal (with 20 pF load capacitance) connected to XI/XO pins or a 40 MHz CMOS oscillator driving the XI pin. When using a crystal, VSSOSC must remain unconnected to PCB ground; when using an oscillator, VSSOSC connects to ground. The FREQSEL[1:0] pins configure the PLL multiplier for this input frequency.

Can the TUSB9261PVP firmware be customized?

Yes-the TUSB9261PVP includes 64 kB of on-chip ROM containing boot code and executes application firmware loaded from external SPI flash memory. TI provides tools and documentation to modify firmware for custom HID interfaces (e.g., one-touch backup), GPIO mappings, PWM LED behavior, and SATA power management policies. The integrated ARM Cortex-M3 enables field-upgradable functionality without hardware changes to the TUSB9261PVP design.

What SATA speeds and features does the TUSB9261PVP support?

The TUSB9261PVP supports SATA Gen1 (1.5 Gbps) and Gen2 (3 Gbps) signaling per SATA Revision 2.6, including Gen1i, Gen1m, Gen2i, and Gen2m modes. It implements AHCI 1.3.1 for native command queuing (NCQ), hot-plug detection, and out-of-band (OOB) link training. The TUSB9261PVP firmware negotiates link speed automatically and supports ATA/ATAPI-8 compliant HDDs, SSDs, and optical drives.

How is power managed on the TUSB9261PVP?

The TUSB9261PVP uses dual power domains: VDD (1.1 V ±5%) for the ARM Cortex-M3 core and USB/SATA PHY logic, and VDD33/VDDA33 (3.3 V ±10%) for I/O buffers and analog circuits. Power sequencing requires VDD to stabilize before or concurrently with VDD33. In USB SuperSpeed active mode, typical current draw is 291 mA @ VDD and 65 mA @ VDD33; suspend current drops to 153 mA @ VDD and 28 mA @ VDD33. GRSTz reset must be held low for ≥2 ms after supplies reach regulation.