Texas Instruments TXS0101DRLR
- Part No.:
- TXS0101DRLR
- Manufacturer:
- Texas Instruments
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
TXS0101DRLR.pdf
- Description:
- IC TRANSLTR BIDIRECTIONAL SOT5X3
- Quantity:
- Payment:

- Shipping:

Inventory:6,181
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TXS0101DRLR from Texas Instruments is a 1-bit bidirectional auto-direction-sensing voltage-level translator IC for open-drain and push-pull logic interfaces, supporting 1.65V–3.6V on A port and 2.3V–5.5V on B port (VCCA ≤ VCCB), with 24Mbps max data rate in push-pull mode and integrated 10kΩ pullups, used in smartphone I/O bridging between 1.8V processors and 3.3V peripherals.
For engineers reviewing the TXS0101DRLR datasheet, TXS0101DRLR pinout, TXS0101DRLR application, or TXS0101DRLR equivalent, this page delivers verified electrical specs, SOT-5X3 package details, real-world timing behavior across VCCA/VCCB combinations, ESD robustness per JESD22, and validated alternative translators for voltage translation design validation.
Technical Context
The TXS0101DRLR employs a pass-gate architecture with edge-rate-accelerating one-shot circuits to enhance low-to-high transition speed without direction-control signals. Its dual-rail design enables automatic bidirectional level shifting between mismatched logic domains while maintaining signal integrity at up to 24Mbps in push-pull mode.
VCCA must be ≤ VCCB during operation; no power-supply sequencing is required, and VCC isolation ensures both ports enter high-impedance state if either supply drops to GND. The OE input-referenced to VCCA-controls global 3-state enable/disable with 200ns enable/disable times.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCCA Range | 1.65V to 3.6V - sets A-port logic threshold and defines minimum compatible controller voltage (e.g., 1.8V ARM core). |
| VCCB Range | 2.3V to 5.5V - supports interface to 2.5V/3.3V/5V peripherals (e.g., I²C EEPROM, GPIO expanders) without external level shifters. |
| Max Data Rate | 24Mbps (push-pull), 2Mbps (open-drain) - determines real-time throughput for high-speed serial links like UART or SPI clock domains. |
| Propagation Delay | 2.4–6.8ns (tPHL/tPLH, VCCA=3.3V/VCCB=3.3V) - ensures sub-7ns latency critical for timing-critical control paths in mobile SoC interconnects. |
| ESD Robustness | B port: ±8kV HBM - enables direct connection to exposed I/O pins in handheld devices without additional protection circuitry. |
| IOFF Current | ±2µA (–40°C to 85°C) - guarantees ultra-low leakage during partial power-down, preserving battery life in always-on sensor subsystems. |
| Integrated Pullups | 10kΩ on A/B ports - eliminates need for external resistors in open-drain applications (e.g., I²C bus), reducing BOM count and PCB area. |
Pinout & Package
SOT-5X3 (DRL) package: 1.6mm × 1.6mm, 0.5mm pitch, 6-pin ultra-small outline with thermal pad - optimized for space-constrained mobile PCBs and automated assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCCA | A-port supply input | Reference rail for A-side logic levels; must be ≤ VCCB; powers internal OE circuitry and A-port pullups. |
| GND | Ground reference | Common return path for both ports; required for proper biasing of pass-gate transistors and ESD protection network. |
| A | Bidirectional I/O (A side) | Connects to 1.65V–3.6V domain; features internal 10kΩ pullup to VCCA; senses direction automatically. |
| B | Bidirectional I/O (B side) | Connects to 2.3V–5.5V domain; features internal 10kΩ pullup to VCCB; supports open-drain or push-pull drivers. |
| OE | Output enable (active-high) | Referenced to VCCA; drives all I/Os into high-impedance when low; requires pull-down resistor for safe power-up state. |
| VCCB | B-port supply input | Reference rail for B-side logic levels; supplies B-port pullups and output stage; must be ≥ VCCA during operation. |
Key Features
| Feature | Design Value |
|---|---|
| No direction-control signal required | Eliminates MCU GPIO overhead and routing complexity in bidirectional buses like I²C or SMBus. |
| VCC isolation | Both A and B ports go high-Z if either VCCA or VCCB = GND - prevents back-powering and latch-up during partial power-down. |
| No power-supply sequencing needed | Either VCCA or VCCB may ramp first - simplifies power management design in multi-rail mobile platforms. |
| Auto-direction sensing with edge acceleration | One-shot PMOS boost circuit reduces rise time by >50% vs passive translation - maintains signal fidelity at 24Mbps. |
| Integrated 10kΩ pullups on both ports | Reduces component count and layout area for open-drain interfaces; avoids external resistor tolerance and parasitic effects. |
Applications
| Smartphone Baseband–PMIC Interface | Tablet Sensor Hub Bridging |
|---|---|
|
Use Scenario: Connecting a 1.8V application processor GPIO bank to a 3.3V power-management IC with open-drain reset and interrupt lines. IC Role / Device Role / Timing Role: Bidirectional level translator enabling reliable handshaking and status polling without direction control or external pullups. Use Value: Eliminates two external 10kΩ resistors and one GPIO dedicated to DIR control, saving 0.5mm² PCB area and simplifying firmware initialization. |
Use Scenario: Interfacing a 2.5V ambient light sensor (I²C open-drain) to a 3.3V sensor hub MCU in a tablet's display subsystem. IC Role / Device Role / Timing Role: Voltage translator ensuring valid logic thresholds on both sides while maintaining I²C bus timing compliance at 400kHz. Use Value: Internal pullups guarantee bus termination without trace-length-dependent RC delays, enabling stable communication over 8cm flex cable runs. |
| Laptop EC–Embedded Controller Bus | Wearable BLE Module I/O Expansion |
|
Use Scenario: Bridging a 3.3V embedded controller (EC) to legacy 5V system management peripherals (e.g., fan tachometer, thermal diode). IC Role / Device Role / Timing Role: Push-pull level shifter supporting 10Mbps SMBus-compatible signaling with sub-7ns propagation delay. Use Value: Enables direct EC-to-peripheral communication without protocol translation or timing margin loss, reducing firmware latency by 12ns per transaction. |
Use Scenario: Extending GPIOs from a 1.8V BLE SoC to drive 3.3V LED indicators and 5V buzzer actuators in compact hearable devices. IC Role / Device Role / Timing Role: Single-channel bidirectional translator providing isolated voltage domains and configurable enable control via OE. Use Value: OE pin allows synchronized shutdown of all extended I/Os during sleep mode, cutting quiescent current to <2µA per channel. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage-level translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TXS0102DRLR | 2-channel version in same DRL package; identical per-channel specs but doubles channel count. | Required when translating two independent signal pairs (e.g., I²C SDA/SCL) without increasing footprint. | Select TXS0102DRLR only if dual-channel functionality is needed; otherwise TXS0101DRLR minimizes cost and routing complexity. |
| TXB0101DRLR | Active-drive architecture (no passive pass-gate); supports VCCA > VCCB; higher drive strength (±20mA vs ±50mA sink only). | Better suited for driving heavy capacitive loads (>30pF) or push-pull-only systems requiring stronger sourcing capability. | Choose TXB0101DRLR for push-pull-heavy designs with >20pF trace capacitance; TXS0101DRLR remains optimal for open-drain I²C and low-power mobile I/O. |
Compared with TXS0101DRLR, TXS0102DRLR offers channel density at identical per-channel performance, while TXB0101DRLR trades auto-direction sensing for active drive and reversed voltage flexibility-making TXS0101DRLR the most power-efficient, area-optimized choice for standard open-drain mobile interfaces.
Availability
TXS0101DRLR is available at Aetrix Electronics and suitable for smartphone, tablet, and wearable electronics requiring stable component supply, fast lead times, and full lifecycle support through obsolescence transitions.
Supply support for TXS0101DRLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions, with decades of expertise in precision logic and interface ICs.
The TXS0101DRLR belongs to TI's NanoFree™ voltage translator family, engineered specifically for space-constrained, low-power mobile and portable electronics where automatic bidirectional level shifting and minimal BOM count are critical.
FAQ
What is the maximum allowable voltage difference between VCCA and VCCB for TXS0101DRLR?
The TXS0101DRLR requires VCCA ≤ VCCB at all times during normal operation. While VCCA may temporarily exceed VCCB during power-up without damage, sustained operation with VCCA > VCCB violates the absolute maximum rating and risks functional failure. For example, pairing VCCA = 3.3V with VCCB = 2.5V is invalid; acceptable combinations include VCCA = 1.8V / VCCB = 3.3V or VCCA = 2.5V / VCCB = 5.0V. Always verify VCCA ≤ VCCB in final schematic review.
Does TXS0101DRLR support I²C bus operation without external pullup resistors?
Yes, TXS0101DRLR integrates 10kΩ pullup resistors on both A and B ports referenced to VCCA and VCCB respectively, enabling direct I²C SDA/SCL translation without external components. This meets standard I²C bus requirements for 100kHz and 400kHz modes when total bus capacitance remains ≤ 400pF. For faster modes or longer traces, external pullups may be added in parallel to reduce effective resistance.
How does the OE pin behave during power-up, and what pull-down value is recommended for TXS0101DRLR?
The OE pin of TXS0101DRLR is referenced to VCCA and must be held low during power-up to ensure all I/Os remain in high-impedance until both VCCA and VCCB are stable. A 10kΩ pull-down resistor to GND is recommended, as it provides sufficient current sinking (≥100µA) to overcome internal weak pulldowns while avoiding excessive loading on the driving source. TI specifies that OE must not be enabled until both supplies reach regulation.
Can TXS0101DRLR translate signals between 5V and 1.8V logic domains?
Yes, TXS0101DRLR supports translation from 1.8V (A port) to 5V (B port) and vice versa, provided VCCA = 1.8V ≤ VCCB = 5V. Its specified VCCA range (1.65V–3.6V) and VCCB range (2.3V–5.5V) fully cover this combination. Measured propagation delay remains ≤6.8ns and ESD robustness holds at ±8kV HBM on the B port, making it suitable for interfacing legacy 5V peripherals with modern low-voltage controllers.
What thermal derating applies to TXS0101DRLR in its SOT-5X3 package at 85°C ambient?
In the DRL (SOT-5X3) package, TXS0101DRLR has a junction-to-ambient thermal resistance (RθJA) of 207.5°C/W. At 85°C ambient and maximum power dissipation (14.4µA × 5.5V ≈ 79µW), junction temperature rise is only ~16.4°C - well below the 150°C absolute maximum. No thermal derating is required for standard operation; however, PCB copper pour under the thermal pad improves heat dissipation by up to 30% in high-density layouts.
TXS0101DRLR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Translator Type:
- Voltage Level
- Channel Type:
- Bidirectional
- Number of Circuits:
- 1
- Channels per Circuit:
- 1
- Voltage - VCCA:
- 1.65 V ~ 3.6 V
- Voltage - VCCB:
- 2.3 V ~ 5.5 V
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- Open Drain, Push-Pull
- Data Rate:
- 24Mbps
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Features:
- Auto-Direction Sensing
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-563, SOT-666
TXS0101DRLR FAQ
1.How can I place an order for TXS0101DRLR through Aetrix?
Please submit a Request for Quotation (RFQ) for TXS0101DRLR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TXS0101DRLR reliable?
The price and inventory of TXS0101DRLR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TXS0101DRLR is usually 5 days.
3.What payment methods are accepted for TXS0101DRLR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TXS0101DRLR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TXS0101DRLR?
TXS0101DRLR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TXS0101DRLR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TXS0101DRLR?
For technical support, including TXS0101DRLR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TXS0101DRLR requirements.
6.How does Aetrix verify that TXS0101DRLR is sourced from the original manufacturer or authorized distributors?
All TXS0101DRLR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TXS0101DRLR meets industry standards.
7.What is the process for return or replacement of TXS0101DRLR?
All TXS0101DRLR units undergo pre-shipment inspection (PSI). If there is an issue with TXS0101DRLR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TXS0101DRLR part is unused and in its original packaging.
Return procedure for TXS0101DRLR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TXS0101DRLR Tags

-
74LVC1T45GW,125
Nexperia USA Inc.
-
74LVCH2T45DC,125
Nexperia USA Inc.

-
SN74LVC1T45DBVR
Texas Instruments

-
SN74LVC1T45DRLR
Texas Instruments

-
SN74LVC1T45DPKR
Texas Instruments

-
SN74LVC2T45DCTR
Texas Instruments

-
74LVC2T45GT,115
Nexperia USA Inc.

-
SN74LVC1T45YZPR
Texas Instruments

-
LSF0102DCUR
Texas Instruments

-
SN74LVC1T45DCKR
Texas Instruments

-
TXS0102DCTR
Texas Instruments

-
FXLP34P5X
onsemi
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
