Texas Instruments UCC21225ANPLT
- Part No.:
- UCC21225ANPLT
- Manufacturer:
- Texas Instruments
- Category:
- Isolators - Gate Drivers
- Package:
- 13-VFLGA
- Datasheet:
-
UCC21225ANPLT.pdf
- Description:
- DGTL ISO 2.5KV 2CH GT DVR 13VLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UCC21225ANPLT from Texas Instruments is a 2.5-kVRMS isolated dual-channel gate driver in LGA-13 package, delivering 4-A peak source and 6-A peak sink output current. It supports dual low-side, dual high-side, or half-bridge configurations with programmable dead time, 19-ns typical propagation delay, and >100-V/ns CMTI - enabling robust switching control for SiC and GaN power stages in high-frequency DC-DC converters.
For engineers reviewing the UCC21225ANPLT datasheet, UCC21225ANPLT pinout, UCC21225ANPLT application, or UCC21225ANPLT equivalent, key selection criteria include its functional isolation architecture, 5-V UVLO threshold per channel, 3–18-V VCCI input range, and LGA-13 thermal performance (RθJA = 98.0°C/W) under industrial temperature conditions (–40°C to +125°C).
Technical Context
The UCC21225ANPLT integrates two independently powered, functionally isolated output drivers (VDDA/VSSA and VDDB/VSSB), each rated for up to 700-VDC working voltage across the isolation barrier. Its internal capacitive isolation barrier achieves 3535-VPK reinforced insulation per DIN V VDE V 0884-11:2017-01 and 2500-VRMS per UL 1577.
Control logic includes TTL/CMOS-compatible inputs (INA, INB), a dedicated disable pin (DIS) with internal pull-down, and a programmable dead-time pin (DT) supporting resistor-based tuning from 0 ns (overlap) to 1.5 µs (RDT = 500 kΩ). UVLO protection is implemented separately on VCCI, VDDA, and VDDB rails with 0.3-V hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 2.5-kVRMS for 1 min (UL 1577); 3535-VPK reinforced (DIN V VDE V 0884-11) |
| Output Drive Strength | 4-A peak source / 6-A peak sink per channel - sufficient for 1200-V SiC MOSFETs at 5-MHz switching |
| Propagation Delay | 19-ns typical (tPDLH/tPDHL) - enables precise timing control in hard-switched topologies |
| Delay Matching | ≤5-ns max between OUTA/OUTB - critical for minimizing shoot-through risk in half-bridge operation |
| CMTI | >100-V/ns - ensures reliable operation in noisy high-dV/dt environments (e.g., motor drives) |
| VCCI Range | 3-V to 18-V - interoperable with 3.3-V microcontrollers and 15-V analog controllers without level-shifting |
| UVLO Thresholds | VDDA/VDDB: 6.0-V turn-on / 5.7-V turn-off; VCCI: 2.7-V turn-on / 2.5-V turn-off - prevents erratic switching during brownout |
Pinout & Package
LGA-13 (5 mm × 5 mm) package with exposed thermal pad; requires solder paste stencil optimization and controlled reflow profile for void-free mounting. Pin 1 (GND) is primary-side reference; pins 11 (VSSA) and 8 (VSSB) are isolated secondary-side grounds.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 GND | Primary-side ground reference | Reference for all input signals (INA, INB, DIS, DT) and VCCI supply |
| 2 INA | Channel A input | TTL/CMOS-compatible; internally pulled low if floating - tie to GND when unused |
| 3 INB | Channel B input | Independent logic input; same threshold and noise immunity as INA |
| 4,7 VCCI | Primary-side supply | Dual-pin configuration for low-inductance decoupling; requires local 0.1-µF ceramic capacitor |
| 5 DIS | Global disable control | Active-high; pulls both outputs low when asserted - essential for safe power sequencing |
| 6 DT | Dead-time programming | Resistor-to-GND sets dead time (0–1500 ns); open = <15 ns; 20-kΩ = ~200 ns |
| 8 VSSB | Secondary-side ground B | Isolated return for VDDB and OUTB; must be separated from VSSA on PCB |
| 9 OUTB | Channel B gate drive output | 6-A sink / 4-A source; connects directly to gate of high-side or low-side FET/IGBT |
| 10 VDDB | Secondary-side supply B | 6.5–25-V rail for OUTB; requires local 1-µF ceramic decoupling to VSSB |
| 11 VSSA | Secondary-side ground A | Isolated return for VDDA and OUTA; galvanically separated from VSSB |
| 12 OUTA | Channel A gate drive output | 6-A sink / 4-A source; independent of OUTB - enables asymmetric drive configurations |
| 13 VDDA | Secondary-side supply A | 6.5–25-V rail for OUTA; decoupled locally to VSSA with low-ESR capacitor |
Key Features
| Feature | Design Value |
|---|---|
| Programmable dead time | Adjustable from 0 ns (overlap mode) to 1.5 µs via single external resistor - eliminates need for external logic or timers |
| Functional isolation between channels | Enables independent VDDA/VSSA and VDDB/VSSB supplies - supports split-rail or floating high-side configurations up to 700-VDC |
| Fast disable response | Sub-50-ns shutdown of both outputs upon DIS assertion - meets IEC 61800-5-2 functional safety requirements |
| Input transient rejection | Rejects noise pulses <5 ns wide - prevents false triggering in EMI-heavy industrial environments |
| Thermal derating support | Integrated safety-limiting curves for IS (50 mA/channel @ 25°C) and PS (0.6 W/channel) - simplifies thermal design for continuous operation |
Applications
| Server Power Supply | Solar DC-AC Inverter |
|---|---|
Use Scenario: 48-V to 12-V intermediate bus converter using synchronous buck topology with 1-MHz switching. IC Role / Device Role / Timing Role: Dual low-side driver controlling parallel MOSFETs; leverages matched propagation delay to minimize conduction loss imbalance. Use Value: 5-ns delay matching reduces current sharing error to <2% across paralleled devices, improving efficiency by 0.4% at full load. |
Use Scenario: Three-phase string inverter stage with 650-V SiC MOSFETs operating at 100 kHz. IC Role / Device Role / Timing Role: Half-bridge driver with programmable dead time set to 200 ns to prevent shoot-through while maintaining high efficiency. Use Value: Resistor-tuned dead time accommodates gate charge variation across production lots, eliminating need for post-manufacturing calibration. |
| Industrial Motor Drive | EV Onboard Charger |
Use Scenario: 7.5-kW servo drive with isolated current sensing and field-oriented control. IC Role / Device Role / Timing Role: Dual high-side driver powering upper-leg IGBTs; uses VSSA/VSSB separation to maintain ±350-V common-mode voltage margin. Use Value: >100-V/ns CMTI ensures clean gate waveforms despite 5-kV/µs bus transients during IGBT turn-off. |
Use Scenario: Bidirectional AC/DC converter in 11-kW OBC using GaN HEMTs in totem-pole PFC stage. IC Role / Device Role / Timing Role: Half-bridge driver with fast disable for fault response; VCCI compatibility with 3.3-V MCU enables direct interface without level shifters. Use Value: 4-A source/6-A sink drive strength sustains 10-ns rise/fall times into 1-nF GaN gate capacitance, enabling >300-kHz PFC operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar isolated dual-channel gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8273BD-D-IS | 2.5-kVRMS isolation; 4-A source/6-A sink; but fixed 100-ns dead time (non-programmable) | Lacks DT pin flexibility - unsuitable where adaptive dead time is required for varying gate charge or temperature drift | Prefer UCC21225ANPLT when dead-time tuning is needed for optimal efficiency across load/temperature |
| ADUM4223BRIZ-RL | 5-kVRMS isolation; 4-A source/6-A sink; but only 25-V VDD max and no integrated UVLO on secondary side | Requires external UVLO circuitry for VDD monitoring - increases BOM count and layout complexity | Choose UCC21225ANPLT for simplified design with built-in per-rail UVLO and higher 25-V VDD rating |
Compared with Si8273BD-D-IS and ADUM4223BRIZ-RL, the UCC21225ANPLT uniquely combines programmable dead time, dual independent secondary supplies with per-rail UVLO, and industry-leading CMTI - making it optimal for high-reliability, high-density power conversion where timing precision and fault resilience are critical.
Availability
UCC21225ANPLT is available at Aetrix Electronics and suitable for server power supplies, solar inverters, industrial motor drives, and EV onboard chargers requiring stable component supply across multi-year production cycles.
Supply support for UCC21225ANPLT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 90 years of innovation in industrial and automotive electronics.
The UCC21225ANPLT belongs to TI's high-performance isolated gate driver product line, engineered specifically for high-efficiency, high-reliability power conversion systems operating at elevated frequencies and voltages - including SiC and GaN-based designs.
FAQ
What is the maximum recommended switching frequency for UCC21225ANPLT?
The UCC21225ANPLT is characterized for reliable operation up to 5 MHz, as confirmed in the device description and supported by its 19-ns propagation delay and 6-ns pulse-width distortion. At 5-MHz operation with 1-nF load, total power dissipation remains within the 1.25-W limit specified in the datasheet, provided thermal design meets RθJA ≤ 98°C/W.
Does UCC21225ANPLT support bootstrap high-side driving?
No, the UCC21225ANPLT does not support bootstrap high-side driving. It requires two independent, isolated secondary supplies (VDDA/VSSA and VDDB/VSSB) for high-side operation. Bootstrap operation would violate its functional isolation architecture and compromise the 700-VDC working voltage rating between VSSA and VSSB.
How is dead time configured on UCC21225ANPLT?
Dead time on UCC21225ANPLT is configured via the DT pin: tying DT to VCCI enables overlap mode; leaving DT open yields <15 ns; connecting a resistor (500 Ω to 500 kΩ) from DT to GND sets dead time as DT(ns) ≈ 10 × RDT(kΩ). A 2.2-nF ceramic capacitor near DT improves noise immunity, as specified in the pin function table.
What safety certifications apply to UCC21225ANPLT?
The UCC21225ANPLT carries VDE certification per DIN V VDE V 0884-11:2017-01 (3535-VPK reinforced insulation) and UL recognition per UL 1577 (2500-VRMS for 1 minute). It also meets GB4943.1-2011 requirements (CQC planned), with 320-VRMS maximum working voltage and pollution degree 2 compliance.
Can UCC21225ANPLT drive both N-channel and P-channel MOSFETs?
Yes, the UCC21225ANPLT can drive both N-channel and P-channel MOSFETs. Its 4-A source / 6-A sink capability and rail-to-rail output swing (e.g., 11.95 V high / 5.5 mV low at VDD = 12 V) provide sufficient gate drive strength and voltage margin for standard logic-level and enhancement-mode devices in low-side or high-side configurations.
UCC21225ANPLT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 13-VFLGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 2500Vrms
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- 30ns, 30ns
- Pulse Width Distortion (Max):
- 6ns
- Rise / Fall Time (Typ):
- 6ns, 7ns
- Current - Output High, Low:
- 4A, 6A
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 3V ~ 18V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 13-VLGA (5x5)
- Approval Agency:
- CQC, CSA, UR, VDE
UCC21225ANPLT FAQ
1.How can I place an order for UCC21225ANPLT through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC21225ANPLT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC21225ANPLT reliable?
The price and inventory of UCC21225ANPLT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC21225ANPLT is usually 5 days.
3.What payment methods are accepted for UCC21225ANPLT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC21225ANPLT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC21225ANPLT?
UCC21225ANPLT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC21225ANPLT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC21225ANPLT?
For technical support, including UCC21225ANPLT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC21225ANPLT requirements.
6.How does Aetrix verify that UCC21225ANPLT is sourced from the original manufacturer or authorized distributors?
All UCC21225ANPLT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC21225ANPLT meets industry standards.
7.What is the process for return or replacement of UCC21225ANPLT?
All UCC21225ANPLT units undergo pre-shipment inspection (PSI). If there is an issue with UCC21225ANPLT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC21225ANPLT part is unused and in its original packaging.
Return procedure for UCC21225ANPLT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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