Texas Instruments UCC21520ADW
- Part No.:
- UCC21520ADW
- Manufacturer:
- Texas Instruments
- Category:
- Isolators - Gate Drivers
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
UCC21520ADW.pdf
- Description:
- DGTL ISO 5.7KV 2CH GT DVR 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:685
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Product details
Overview
UCC21520ADW from Texas Instruments is a reinforced-isolated dual-channel gate driver IC designed to drive power MOSFETs, IGBTs, and SiC MOSFETs in high-voltage switching topologies. It delivers 4A peak source and 6A peak sink output current per channel, features 33ns typical propagation delay, 6ns max pulse-width distortion, and >125V/ns common-mode transient immunity (CMTI), enabling robust operation in HEV/BESS battery chargers and isolated DC-DC converters.
For engineers reviewing the UCC21520ADW datasheet, UCC21520ADW pinout, UCC21520ADW application, or UCC21520ADW equivalent, key selection criteria include its 5.7kVRMS reinforced isolation rating, programmable dead time via external resistor, dual independent UVLO thresholds (5V or 8V options), and SOIC-16 DW package with functional isolation between secondary-side drivers.
Technical Context
The UCC21520ADW integrates two independently isolated output channels separated by a reinforced 5.7kVRMS barrier, supporting up to 1500VDC working voltage between VSSA and VSSB. Its input side (VCCI, INA/INB, DIS, DT) is galvanically isolated from both output sides (VDDA/VSSA/OUTA and VDDB/VSSB/OUTB), with internal functional isolation enabling asymmetric supply configurations.
It implements TTL/CMOS-compatible inputs with internal pull-downs, programmable dead time (80–600ns via RDT), fast disable response (<100ns), and fail-safe logic that forces both outputs low on primary-side failure. UVLO protection applies separately to VCCI (2.7V rising), VDDA, and VDDB (5.7V or 7.7V rising depending on variant).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Isolation Rating | 5.7kVRMS for 1 minute per UL 1577; 8000VPK reinforced per VDE 0884-17 - enables safety-certified designs in industrial and EV infrastructure |
| Output Drive Strength | 4A peak source / 6A peak sink per channel - sufficient to drive high-Qg SiC MOSFETs at >5MHz switching frequencies |
| Propagation Delay | 33ns typical (26–45ns over temp) - supports tight timing control in high-frequency resonant and phase-shifted topologies |
| CMTI | >125V/ns - ensures reliable operation under fast dV/dt transients in 1500VDC bus systems |
| Dead Time Range | 80–600ns programmable via 2–500kΩ resistor on DT pin - allows precise optimization of shoot-through prevention in half-bridge configurations |
| Operating Temp | –40°C to +150°C junction - supports placement near power stages in thermally constrained motor drives and solar inverters |
| VCCI Range | 3V to 18V - interfaces directly with 3.3V microcontrollers, 5V analog controllers, and 12V FPGA I/O without level-shifting |
Pinout & Package
DW package: 16-pin SOIC (10.30mm × 7.50mm), surface-mount, creepage/clearance >8mm, reinforced isolation barrier between primary and secondary sides.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INA, INB | Primary-side digital input | TTL/CMOS-compatible control signals for Channel A/B; internally pulled low if floating - requires grounding when unused for noise immunity |
| DIS | Global disable input | Active-high shutdown of both outputs; internally pulled low - tie to GND if unused; bypass with ~1nF capacitor for MCU interface |
| DT | Dead time programming | Resistor-to-GND sets dead time (80–600ns); tied to VCCI enables overlap - must not float; add ≤1nF ceramic cap for noise rejection |
| VCCI | Primary-side supply | 3–18V input powering logic and isolator transmitter; dual pins (3 & 8) internally shorted - decouple locally with low-ESR/ESL capacitor |
| GND | Primary-side reference | Ground return for all primary-side signals and VCCI - must be star-connected and separated from secondary grounds |
| VDDA, VDDB | Secondary-side supplies | Up to 25V per channel; independent 5V or 8V UVLO options - enable asymmetric rail usage (e.g., VDDA=15V, VDDB=20V) |
| OUTA, OUTB | Gate drive outputs | Push-pull outputs driving FET/IGBT gates; 4A/6A peak; low 0.55Ω pull-down resistance minimizes Miller turn-off delay |
| VSSA, VSSB | Secondary-side grounds | Independent ground references per channel; rated for ±1500V differential - enables split-bus or floating-leg configurations |
| NC (Pins 7,12,13) | No connect | No internal connection - leave unconnected; do not route or solder |
Key Features
| Feature | Design Value |
|---|---|
| Reinforced Isolation | 5.7kVRMS UL 1577 + 8000VPK VDE 0884-17 certification - eliminates need for external isolation components in safety-compliant AC-DC and EV charging designs |
| Programmable Dead Time | Adjustable 80–600ns via single external resistor - replaces discrete RC networks and simplifies PCB layout in half-bridge and three-phase inverter gate drive |
| High CMTI & Surge Immunity | >125V/ns CMTI + 10kV surge rating - maintains signal integrity during lightning-induced transients and fast-switching EMI in industrial UPS and motor drives |
| Dual Independent UVLO | Separate 5V or 8V UVLO on VDDA/VDDB - prevents erratic switching during brown-out conditions in multi-rail power stages |
| Fail-Safe Logic | Primary-side fault forces both outputs low - avoids shoot-through during controller lockup or communication loss in critical power conversion systems |
Applications
| HEV/BESS Battery Chargers | Isolated DC-DC Converters |
|---|---|
Use Scenario: Bidirectional CLLLC resonant converter in 800V EV fast-charging station with SiC MOSFETs. IC Role / Device Role / Timing Role: Dual-channel isolated gate driver controlling high-side and low-side SiC switches in primary and secondary LLC half-bridges. Use Value: 33ns propagation delay matching and 6ns pulse-width distortion ensure precise zero-voltage switching (ZVS) across temperature, improving efficiency above 97%. | Use Scenario: 3.3kW telecom rectifier using phase-shifted full-bridge topology with 100kHz+ switching. IC Role / Device Role / Timing Role: Isolated driver for primary-side FETs with independent VDDA/VDDB rails and programmable dead time. Use Value: 125V/ns CMTI prevents false triggering during 10kV surge events on AC input, meeting IEC 61000-4-5 Level 4 immunity requirements. |
| Motor Drives | Solar Inverters |
Use Scenario: 15kW traction inverter for electric bus with dual 3-phase legs and active front-end rectification. IC Role / Device Role / Timing Role: Gate driver for IGBT modules in inverter leg with functional isolation between phases. Use Value: 1500VDC channel-to-channel working voltage enables direct connection to 1200V IGBTs without additional isolation barriers. | Use Scenario: Central string inverter with 1500V DC input and transformerless topology requiring reinforced isolation. IC Role / Device Role / Timing Role: Isolated driver for high-voltage SiC half-bridge in DC-AC stage with independent UVLO monitoring. Use Value: UL 1577 and VDE 0884-17 certifications satisfy grid-tie safety standards (UL 1741, IEC 62109) without external optocouplers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si8273BD-D-IS | 3.3A/3.3A drive strength; 40ns propagation delay; 5kVRMS isolation; no programmable dead time | Lacks DT pin and independent VDD UVLO options - requires external dead-time generation and tighter supply regulation | Preferred where lower drive current suffices and cost sensitivity outweighs design flexibility |
| ADUM4223BRIZ | 4A/6A drive; 5.7kVRMS; but only 25V max VDD; fixed 100ns dead time; no DT pin | Fixed dead time limits optimization in variable-frequency resonant converters; lower VDD headroom restricts high-VGS SiC use | Selected when board space is constrained and dead time is stable across operating conditions |
Compared with Si8273BD-D-IS and ADUM4223BRIZ, the UCC21520ADW provides superior design flexibility through its resistor-programmable dead time, dual UVLO options, and higher 25V VDD capability - making it optimal for high-efficiency, high-density SiC-based power converters requiring adaptive timing control.
Availability
UCC21520ADW is available at Aetrix Electronics and suitable for HEV/BESS battery chargers, isolated DC-DC power supplies, and motor drive inverters requiring stable component supply, long-term lifecycle support, and certified reinforced isolation.
Supply support for UCC21520ADW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability isolation solutions.
The UCC21520ADW belongs to TI's reinforced-isolated gate driver product line, engineered specifically for high-voltage, high-frequency power conversion systems including EV charging, industrial motor control, and renewable energy inverters.
FAQ
What is the isolation voltage rating of the UCC21520ADW?
The UCC21520ADW has a 5.7kVRMS isolation rating per UL 1577 (1-minute test) and 8000VPK reinforced isolation per DIN EN IEC 60747-17 (VDE 0884-17). These ratings apply to the reinforced barrier between primary (VCCI/GND/inputs) and secondary (VDDA/VSSA/OUTA and VDDB/VSSB/OUTB) sides. The UCC21520ADW also supports 1500VDC working voltage between VSSA and VSSB due to internal functional isolation.
Does the UCC21520ADW support both 5V and 8V UVLO thresholds on VDDA and VDDB?
Yes, the UCC21520ADW supports two UVLO variants: the UCC21520 (8V UVLO) and UCC21520A (5V UVLO). The UCC21520ADW is the 5V UVLO version - its VDDA and VDDB rising UVLO threshold is 6.0V (min 5.7V, max 6.3V), with 0.3V hysteresis. This allows reliable operation with 12V or 15V gate drive rails while preventing turn-on during brown-out conditions.
How is dead time programmed on the UCC21520ADW?
Dead time on the UCC21520ADW is programmed using an external resistor (RDT) between the DT pin and GND. The relationship is DT(ns) = 10 × RDT(kΩ), yielding 80–600ns for 2–500kΩ. Tying DT to VCCI enables overlap mode. A ≤1nF ceramic capacitor should be placed close to DT for noise immunity. Leaving DT floating is not recommended.
What is the maximum switching frequency supported by the UCC21520ADW?
The UCC21520ADW is specified to drive power devices up to 5MHz, based on its 33ns typical propagation delay, 20ns minimum pulse width, and fast 6–16ns rise/fall times (with 1.8nF load). Real-world usable frequency depends on gate charge, layout, and thermal management - for example, it reliably drives 1200V SiC MOSFETs in 300–500kHz resonant converters with ZVS.
Can the UCC21520ADW drive both high-side and low-side configurations in the same design?
Yes, the UCC21520ADW supports flexible configuration: each channel can operate as high-side, low-side, or half-bridge driver. Its dual isolated outputs (OUTA/VSSA and OUTB/VSSB) allow independent referencing - e.g., OUTA can drive a high-side switch referenced to a floating 400V bus, while OUTB drives a low-side switch referenced to system ground. Internal functional isolation ensures safe operation up to 1500VDC between VSSA and VSSB.
UCC21520ADW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Last Time Buy
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 5700Vrms
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- 30ns, 30ns
- Pulse Width Distortion (Max):
- 6ns
- Rise / Fall Time (Typ):
- 6ns, 7ns
- Current - Output High, Low:
- 4A, 6A
- Current - Peak Output:
- -
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 6.5V ~ 25V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
- Approval Agency:
- CQC, CSA, UR, VDE
UCC21520ADW FAQ
1.How can I place an order for UCC21520ADW through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC21520ADW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC21520ADW reliable?
The price and inventory of UCC21520ADW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC21520ADW is usually 5 days.
3.What payment methods are accepted for UCC21520ADW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC21520ADW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC21520ADW?
UCC21520ADW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC21520ADW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC21520ADW?
For technical support, including UCC21520ADW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC21520ADW requirements.
6.How does Aetrix verify that UCC21520ADW is sourced from the original manufacturer or authorized distributors?
All UCC21520ADW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC21520ADW meets industry standards.
7.What is the process for return or replacement of UCC21520ADW?
All UCC21520ADW units undergo pre-shipment inspection (PSI). If there is an issue with UCC21520ADW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC21520ADW part is unused and in its original packaging.
Return procedure for UCC21520ADW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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