Texas Instruments UCC21540DWK
- Part No.:
- UCC21540DWK
- Manufacturer:
- Texas Instruments
- Category:
- Isolators - Gate Drivers
- Package:
- 14-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
UCC21540DWK.pdf
- Description:
- DGTL ISO 5.7KV 2CH GT DVR 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,123
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UCC21540DWK from Texas Instruments is a reinforced-isolation dual-channel gate driver IC designed for high-voltage power stage control in isolated half-bridge, dual low-side, or dual high-side configurations. It delivers 4 A peak source and 6 A peak sink output current, supports up to 18 V VDD drive supply with 8 V UVLO, achieves ≥125 V/ns CMTI, and features resistor-programmable dead time - enabling robust gate driving of Si MOSFETs, IGBTs, and GaN transistors in 1.7 kV+ bus systems.
For engineers reviewing the UCC21540DWK datasheet, UCC21540DWK pinout, UCC21540DWK application, or UCC21540DWK equivalent, this page provides verified functional identity, SOIC-14 package mapping with 3.3 mm channel-to-channel spacing, confirmed switching parameters (33 ns typical propagation delay, ≤6 ns pulse-width distortion), safety certifications (5700 VRMS UL, 8000 VPK VDE), and validated alternative part options for industrial power and motor drive designs.
Technical Context
The UCC21540DWK integrates two independent isolated output channels separated by a 5.7 kVRMS reinforced insulation barrier, with input-side logic referenced to VCCI/GND and each output channel powered separately via VDDA/VSSA and VDDB/VSSB. Its architecture supports flexible configuration (half-bridge, dual high-side, or dual low-side) without internal cross-conduction risk due to programmable dead time and simultaneous disable functionality.
It implements TTL/CMOS-compatible inputs with internal pull-down, −5 V transient tolerance on INA/INB for 50 ns, and dual-stage UVLO protection on both VCCI (2.7 V rising) and VDDA/VDDB (8.5 V rising). The 3.3 mm minimum creepage between VSSA and VSSB in the DWK package enables higher DC-link voltage operation while maintaining compliance with DIN EN IEC 60747-17 and UL 1577.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Peak Output Current | 4 A source / 6 A sink per channel - sufficient to drive 1200 V SiC MOSFETs or 650 V GaN HEMTs at >1 MHz switching frequencies. |
| Propagation Delay | 33 ns typical - enables precise timing control in high-frequency isolated DC-DC converters and servo motor drives. |
| Pulse-Width Distortion | ≤6 ns maximum - ensures matched turn-on/turn-off timing across channels, critical for minimizing shoot-through in half-bridge topologies. |
| CMTI | >125 V/ns - maintains signal integrity during fast dV/dt transients in high-power inverters and EV traction systems. |
| VDD UVLO Threshold | 8.5 V (rising), 7.9 V (falling) - prevents erratic gate drive during brown-out conditions in industrial 12–15 V auxiliary supplies. |
| Isolation Rating | 5700 VRMS (UL), 8000 VPK (VDE) - certified reinforced isolation suitable for 1000 VAC mains-connected equipment per IEC 62368-1. |
| Channel Spacing | 3.3 mm min. VSSA–VSSB clearance - supports ≥1850 VDC working voltage between secondary-side grounds in high-bus applications. |
Pinout & Package
UCC21540DWK uses a 14-pin wide-body SOIC (DWK) package with 3.3 mm minimum channel-to-channel spacing. Pin 12 and pin 13 are omitted versus the SOIC-16 DW variant, optimizing creepage for high-voltage isolation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INA, INB | Input logic signals | TTL/CMOS-compatible inputs with internal pull-down; tied low when unused to prevent noise-induced switching. |
| DIS | Global disable control | Active-high shutdown of both outputs - recommended to tie to GND if unused for improved noise immunity. |
| DT | Dead-time programming | Resistor-to-GND sets dead time (10 × RDT ns); bypassed with ≤1 nF capacitor to suppress EMI coupling. |
| VCCI | Primary-side supply | 3–18 V input supply powering logic and isolation transmitter; decoupled locally to GND with low-ESR capacitor. |
| VDDA, VDDB | Secondary-side driver supplies | 9.2–25 V per channel - powers gate drive stages independently; each requires local decoupling to respective VSSA/VSSB. |
| OUTA, OUTB | Gate drive outputs | Push-pull outputs capable of 4 A/6 A peak current - directly connect to power device gates with minimal external components. |
| VSSA, VSSB | Secondary-side grounds | Independent return paths for each driver channel; 3.3 mm spacing enables ≥1850 VDC differential voltage capability. |
| GND | Primary-side reference | Logic and isolation transmitter ground - must be separated from power ground planes to maintain CMTI performance. |
Key Features
| Feature | Design Value |
|---|---|
| Reinforced Isolation Barrier | 5.7 kVRMS with ≥125 V/ns CMTI - eliminates need for external optocouplers or discrete isolation in IEC 62368-1-compliant 1000 VAC systems. |
| Programmable Dead Time | Adjustable 80–600 ns via single external resistor - enables precise overlap control without MCU intervention in hard-switched converters. |
| High-Voltage Transient Tolerance | −5 V input spikes tolerated for 50 ns - protects against Miller-induced false triggering during high-dV/dt switching events. |
| Dual Independent Outputs | Separate VDDA/VSSA and VDDB/VSSB supplies - allows asymmetric gate drive voltages (e.g., +15 V/−5 V) for enhanced SiC/GaN turn-off control. |
| UVLO Protection | Independent monitoring of VCCI (2.7 V) and VDDA/VDDB (8.5 V) - prevents partial operation that could damage power devices during supply ramp-up. |
Applications
| Industrial Motor Drives | Solar String Inverters |
|---|---|
|
Use Scenario: Driving dual IGBT half-bridge in 690 VAC three-phase VFDs with active short-circuit protection. IC Role / Device Role: Dual high-side gate driver with synchronized disable and programmable dead time to prevent shoot-through during fault recovery. Use Value: 3.3 mm VSSA–VSSB spacing enables direct integration into 1200 VDC bus designs without additional creepage barriers. |
Use Scenario: Controlling back-to-back SiC MOSFETs in transformerless string inverters operating at 1500 VDC bus. IC Role / Device Role: Isolated dual low-side driver with 125 V/ns CMTI to reject common-mode noise from PV array leakage currents. Use Value: 4 A/6 A peak current supports fast SiC switching at 100 kHz while maintaining <6 ns pulse-width distortion. |
| Server AC-DC Power Supplies | Railway Traction Converters |
|
Use Scenario: Driving LLC resonant converter synchronous rectifiers in 48 V intermediate bus architectures. IC Role / Device Role: Dual low-side gate driver with independent VDDA/VDDB supplies enabling adaptive gate voltage control per phase. Use Value: Resistor-programmable dead time eliminates need for complex timing compensation in multi-phase interleaved designs. |
Use Scenario: Gate driving 3300 V IGBT modules in 4-quadrant traction inverters for metro rolling stock. IC Role / Device Role: Reinforced-isolation dual-channel driver with 8000 VPK surge rating for EN 50155-compliant high-reliability systems. Use Value: Certified VDE 0884-17 and UL 1577 compliance ensures long-term reliability under railway-grade thermal cycling and vibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel isolated gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC21540DW | SOIC-16 package with 16 pins; no pin 12/13 removal; 1500 VDC max VSSA–VSSB rating. | Limited to ≤1500 VDC bus systems; requires larger PCB footprint but offers NC pins for layout flexibility. | Select UCC21540DW when board space permits and 3.3 mm channel spacing is not required for system-level creepage. |
| UCC21542DWK | Same SOIC-14 DWK package and 3.3 mm spacing, but lacks resistor-programmable dead time circuitry. | Requires MCU-based dead time insertion; suitable where timing precision is managed externally or overlap is acceptable. | Choose UCC21542DWK only when dead time control is implemented in firmware and cost reduction is prioritized over analog flexibility. |
Compared with UCC21540DWK, UCC21540DW trades channel spacing for pin count and layout margin, while UCC21542DWK removes analog dead time to reduce BOM count - making UCC21540DWK the optimal choice for high-reliability, high-bus industrial systems requiring hardware-enforced timing safety.
Availability
UCC21540DWK is available at Aetrix Electronics and suitable for industrial motor drives, solar inverters, and server power supplies requiring stable component supply with full safety certification traceability and long-term lifecycle support.
Supply support for UCC21540DWK includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 90 years of innovation in high-reliability industrial and automotive solutions.
The UCC2154x family was engineered specifically for high-efficiency, high-voltage isolated power conversion and motor control - delivering reinforced isolation, programmable timing, and robust transient immunity in compact SOIC packages.
FAQ
What is the maximum allowable VSSA–VSSB differential voltage for UCC21540DWK?
The UCC21540DWK supports up to 1850 VDC between VSSA and VSSB due to its 3.3 mm minimum channel-to-channel spacing and reinforced isolation structure. This rating is validated per DIN EN IEC 60747-17 and enables direct use in 1500 VDC solar and 690 VAC motor drive systems without external creepage enhancement. Always verify PCB layout meets IPC-2221B minimum spacing rules for the target pollution degree.
Does UCC21540DWK support asymmetric gate drive voltages?
Yes, UCC21540DWK supports asymmetric gate drive through independent VDDA/VSSA and VDDB/VSSB supplies - allowing different positive/negative rail voltages per channel (e.g., +15 V/−5 V for SiC turn-off control). Each secondary-side supply must be decoupled locally to its respective ground, and UVLO thresholds apply individually to VDDA and VDDB.
How is dead time programmed on UCC21540DWK?
Dead time on UCC21540DWK is set by connecting a resistor (RDT) between the DT pin and GND, using the formula DT (ns) = 10 × RDT (kΩ). For example, a 20 kΩ resistor yields ~200 ns dead time. TI recommends placing a ≤1 nF ceramic capacitor close to the DT pin to suppress noise coupling, and never leaving DT floating.
What safety certifications does UCC21540DWK hold?
UCC21540DWK is certified to 5700 VRMS isolation for 1 minute per UL 1577 and 8000 VPK reinforced isolation per DIN EN IEC 60747-17 (VDE 0884-17), with additional CQC certification per GB4943.1-2022. These ratings are tested and qualified across temperature and lifetime, supporting use in safety-critical industrial and transportation equipment.
Can UCC21540DWK drive GaN transistors effectively?
Yes, UCC21540DWK is explicitly characterized for GaN transistor drive, delivering 4 A peak source and 6 A peak sink current with ≤33 ns propagation delay and ≤6 ns pulse-width distortion - enabling clean, high-speed switching of 650 V GaN HEMTs up to 1 MHz. Its −5 V input transient tolerance also mitigates Miller-induced turn-on in cascode GaN configurations.
UCC21540DWK Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Last Time Buy
- Technology:
- Capacitive Coupling
- Number of Channels:
- 2
- Voltage - Isolation:
- 5700Vrms
- Common Mode Transient Immunity (Min):
- 100V/ns
- Propagation Delay tpLH / tpHL (Max):
- 40ns, 40ns
- Pulse Width Distortion (Max):
- 5.5ns
- Rise / Fall Time (Typ):
- 5ns, 6ns
- Current - Output High, Low:
- 4A, 6A
- Current - Peak Output:
- 4A, 6A
- Voltage - Forward (Vf) (Typ):
- -
- Current - DC Forward (If) (Max):
- -
- Voltage - Output Supply:
- 9.2V ~ 18V
- Grade:
- -
- Qualification:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
- Approval Agency:
- CQC, UL, VDE
UCC21540DWK FAQ
1.How can I place an order for UCC21540DWK through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC21540DWK on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC21540DWK reliable?
The price and inventory of UCC21540DWK are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC21540DWK is usually 5 days.
3.What payment methods are accepted for UCC21540DWK?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC21540DWK transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC21540DWK?
UCC21540DWK orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC21540DWK order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC21540DWK?
For technical support, including UCC21540DWK datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC21540DWK requirements.
6.How does Aetrix verify that UCC21540DWK is sourced from the original manufacturer or authorized distributors?
All UCC21540DWK products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC21540DWK meets industry standards.
7.What is the process for return or replacement of UCC21540DWK?
All UCC21540DWK units undergo pre-shipment inspection (PSI). If there is an issue with UCC21540DWK, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC21540DWK part is unused and in its original packaging.
Return procedure for UCC21540DWK:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UCC21540DWK Tags
-
TLP152(TPL,E
Toshiba Semiconductor and Storage

-
HT0740LG-G
Microchip Technology

-
FOD8314TR2
onsemi

-
1EDI60N12AFXUMA1
Infineon Technologies

-
1EDB7275FXUMA1
Infineon Technologies

-
UCC5350MCDR
Texas Instruments

-
2EDB7259KXUMA1
Infineon Technologies

-
UCC5304DWVR
Texas Instruments

-
SI8261BBC-C-ISR
Skyworks Solutions Inc.

-
HT0440LG-G
Microchip Technology

-
HCPL-0302-500E
Broadcom Limited

-
STGAP2HSCMTR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

