Texas Instruments UCC28019DRG4

Overview

UCC28019DRG4 from Texas Instruments is an 8-pin continuous conduction mode (CCM) active Power Factor Correction (PFC) controller for boost topology converters. It delivers fixed 65-kHz switching, 97% maximum duty cycle, and operates across universal AC input (85–265 VAC) in 100 W to >2 kW systems. Its average current mode control enables low-distortion input current shaping without line voltage sensing-ideal for server power supplies requiring high efficiency and EN55022-compliant EMI performance.

For engineers reviewing the UCC28019DRG4 datasheet, UCC28019DRG4 pinout, UCC28019DRG4 application, or UCC28019DRG4 equivalent, key selection considerations include its integrated 1.5-A source / 2.0-A sink gate driver, UVLO thresholds (10.5 V turn-on, 9.5 V turn-off), open-loop protection at 0.82 V on VSENSE, soft over-current threshold of –0.73 V on ISENSE, and 5.00 V internal reference with ±1% tolerance over temperature.

Technical Context

The UCC28019DRG4 implements dual-loop average current mode control: the inner current loop uses transconductance gain g_mi = 0.95 mS to shape input current, while the outer voltage loop employs g_mv = 42 µS and a trimmed 5.00 V reference for output regulation. Its oscillator is internally fixed at 65 kHz ±5% and trimmed for EN55022 compliance by placing fundamental and second harmonic noise below 150 kHz.

System-level protection includes cycle-by-cycle peak current limiting (–1.08 V ISENSE threshold), soft over-current detection (–0.73 V), input brown-out protection (VINS enable at 1.5 V, disable at 0.82 V), output over-voltage (5.25 V) and under-voltage (4.75 V) detection, and open-loop/standby activation at 0.82 V on VSENSE-each with dedicated internal comparators and fault logic.

Key Specifications

Pinout & Package

UCC28019DRG4 is housed in an SOIC-8 (D) package with standard 1.27 mm pitch, RoHS-compliant, green molding compound. Thermal resistance θ_JA = 160°C/W at T_A = 25°C.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CCM boost PFC controller applications.

Compared with UCC28019DRG4, UCC28070D offers higher integration for multi-phase systems but increases design complexity, while L6562ADTR simplifies layout at the expense of protection granularity and dynamic performance-making UCC28019DRG4 the optimal balance for single-phase 100 W–2 kW industrial and telecom PFC.

Availability

UCC28019DRG4 is available at Aetrix Electronics and suitable for server power supplies, telecom rectifiers, and industrial motor drives requiring stable component supply, long-term lifecycle support, and traceable sourcing for production programs.

Supply support for UCC28019DRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in power conversion and energy-efficient design.

The UCC28019DRG4 belongs to TI's active PFC controller product line, engineered specifically for cost-effective, high-reliability single-phase CCM boost PFC in 100 W–2 kW applications-emphasizing simplicity, protection robustness, and EMI compliance.

FAQ

What is the purpose of the VINS pin on the UCC28019DRG4?

The VINS pin on the UCC28019DRG4 provides dedicated input AC voltage sensing for independent brown-out protection. It enables startup when voltage exceeds 1.5 V and disables operation when voltage falls below 0.82 V-decoupling protection from the VCC supply. This ensures reliable shutdown during low-line conditions even if the auxiliary supply remains active, preventing overheating in the boost stage. The VINS bias current is <0.1 µA, minimizing set-point error in the resistor-divider network.

How does the UCC28019DRG4 achieve power factor correction without sensing the AC line voltage?

The UCC28019DRG4 achieves power factor correction using average current mode control with inherent line-voltage feedforward derived from the VSENSE and VINS signals-not direct line sensing. The controller shapes the input current by comparing the sensed inductor current (ISENSE) against a reference proportional to the rectified line voltage, reconstructed internally via the VINS signal and output voltage feedback. This eliminates external line-sensing components while maintaining <5% THD across universal AC inputs.

What protection features does the UCC28019DRG4 provide for the PFC output stage?

The UCC28019DRG4 provides comprehensive output protection including over-voltage protection (OVP) triggered at 5.25 V on VSENSE, under-voltage detection (UVD) at 4.75 V, open-loop protection (OLP) that pulls VSENSE low via a 100 nA internal sink if feedback disconnects, and user-controlled standby activation below 0.77 V. All protections disable the GATE output immediately and place the controller in a low-current state-ensuring safe shutdown without external circuitry.

Can the UCC28019DRG4 operate from a bootstrap VCC supply?

No, the UCC28019DRG4 is not designed to operate from a bootstrap VCC supply. TI explicitly recommends powering it from a regulated auxiliary supply due to its minimal UVLO hysteresis (1.0 V) and sensitivity to VCC ripple. A bootstrap supply-fed through a high-value resistor and hold-up capacitor-would require impractically large capacitance to maintain VCC above 9.5 V during startup and light-load conditions, risking unreliable operation or premature shutdown.

What is the role of Enhanced Dynamic Response (EDR) in the UCC28019DRG4?

Enhanced Dynamic Response (EDR) in the UCC28019DRG4 accelerates recovery from large load transients by injecting additional current into the VCOMP pin when VSENSE falls below 95% of the 5.00 V reference. This temporarily boosts the voltage loop's effective transconductance, reducing output voltage dip and settling time without compromising steady-state stability. EDR is automatically disabled during soft-start and re-enabled once regulation is achieved.