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Texas Instruments UCC28060DG4
- Part No.:
- UCC28060DG4
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
UCC28060DG4.pdf
- Description:
- IC PFC CTRL TRANS 500KHZ 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:155
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Product details
Overview
UCC28060DG4 from Texas Instruments is a dual-phase transition-mode (TM) power factor correction (PFC) controller with Natural Interleaving™ architecture, designed for 100–800 W AC-DC front-end stages. It delivers 1-A source/1.8-A sink gate drive capability, operates across –40°C to +125°C, and integrates fail-safe over-voltage protection (OVP) using dual-sense inputs (VSENSE and HVSEN) for high-reliability industrial and consumer power supplies.
For engineers reviewing the UCC28060DG4 datasheet, UCC28060DG4 pinout, UCC28060DG4 application, or UCC28060DG4 equivalent, this page provides verified technical context on interleaved TM PFC control, zero-current detection timing, phase management via PHB, PWM on-time scaling (KTH/KTL), and FailSafe OVP implementation - all critical for EMI reduction, light-load efficiency, and system-level fault tolerance in LCD/Plasma TV and server power designs.
Technical Context
The UCC28060DG4 implements a master-master Natural Interleaving™ architecture where both phases operate synchronously at the same frequency without slave dependency, enabling inherently matched on-times (±6% over line range) and faster transient response. Its sensorless current shaping eliminates external current sense transformers, while inrush-safe limiting prevents MOSFET conduction during startup.
FailSafe OVP uses independent thresholds on VSENSE (6.45 V rising) and HVSEN (4.87 V rising) with separate hysteresis and fault latching, protecting against single-point voltage-sensing failures. Phase management is controlled via PHB input, which dynamically switches between two-phase (interleaved) and single-phase operation based on line voltage and COMP voltage, optimizing light-load efficiency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Operating Range | 14–21 V: Powers internal circuitry and gate drivers; clamped at 24 V to prevent damage. |
| Gate Drive Strength | 1-A source / 1.8-A sink: Directly drives high-side MOSFET gates without external buffers in 600-W designs. |
| VSENSE Regulation Voltage | 6.00 V ±0.15 V: Sets output DC bus target (e.g., 400 VDC via resistor divider); enables precise regulation stability. |
| Zero-Cross Detection Thresholds | Falling: 1.0 V, Rising: 1.68 V: Enables accurate inductor current zero-crossing detection for TM boundary control. |
| FailSafe OVP Thresholds | VSENSE: 6.45 V, HVSEN: 4.87 V - redundant sensing paths prevent catastrophic overvoltage due to single-failure modes. |
| Minimum Switching Period | 2.2 µs (typ): Determines maximum switching frequency (~455 kHz); set by TSET resistor (133 kΩ typical). |
| Thermal Shutdown | 160°C (rising), 140°C (falling): Hysteresis prevents oscillation; protects silicon during overload or poor heatsinking. |
Pinout & Package
UCC28060DG4 is housed in a SOIC-16 (D) package with exposed pad thermal enhancement, rated for –40°C to +125°C operation and 140°C/W junction-to-ambient thermal resistance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (ZCDB) | Phase B zero-current detect input | Detects inductor current zero-crossing for phase B; falling edge triggers GDB turn-on; clamped 0–3 V. |
| 2 (VSENSE) | Output voltage feedback input | Compares regulated 400 VDC bus to 6 V reference; error signal drives COMP amplifier for loop control. |
| 3 (TSET) | PWM on-time programming input | Resistor to AGND sets KT scaling factor (1.35 µs/V typ) and minimum period (2.2 µs typ). |
| 4 (PHB) | Phase B enable/disable control | Logic input selecting two-phase (interleaved) or single-phase mode; thresholds vary with VINAC range. |
| 5 (COMP) | Error amplifier output | Transconductance output (96 µS typ); on-time ∝ (VCOMP – 0.125 V); soft-start requires discharge below 0.5 V. |
| 6 (AGND) | Analog ground reference | Return for compensation network, VREF, and analog signals; must be isolated from PGND except at single point. |
| 7 (VINAC) | Rectified AC input voltage sense | Detects brownout (1.39 V) and line range (3.45 V rising); enables adaptive ramp rate and filter timing. |
| 8 (HVSEN) | High-voltage output sense | Redundant OVP path; also enables downstream converter when within 2.5 V window; must stay ≥0.8 V. |
| 9 (PWMCNTL) | Open-drain power-good logic output | Low when HVSEN valid and ZCD inputs active; used to enable secondary-stage controllers or sequencing logic. |
| 10 (CS) | Current sense input | Cycle-by-cycle overcurrent protection; threshold –0.20 V rising; blanked 100 ns after GDx fall edge. |
| 11 (GDB) | Phase B gate driver output | 1.8-A sink / 1-A source; 0.3 V low, 13 V high (VCC = 16 V); rise/fall time <30 ns with 1 nF load. |
| 12 (VCC) | Bias supply input | 14–21 V regulated input; draws 8 mA enabled, 200 µA disabled; bypassed with 0.1 µF ceramic to PGND. |
| 13 (PGND) | Power ground return | Return path for gate drivers and CS; routed separately from AGND to minimize noise coupling into analog circuits. |
| 14 (GDA) | Phase A gate driver output | Identical specs to GDB; outputs synchronized with ZCDA falling edge; supports interleaved current ripple cancellation. |
| 15 (VREF) | 6 V precision reference output | Stable 6.00 V ±6 mV; supplies <2 mA total; bypassed with 0.1 µF ceramic to AGND for low-noise operation. |
| 16 (ZCDA) | Phase A zero-current detect input | Same function as ZCDB; falling edge triggers GDA turn-on; ensures boundary conduction mode per phase. |
Key Features
| Feature | Design Value |
|---|---|
| Natural Interleaving™ architecture | Master-master dual-phase synchronization eliminates slave dependency, ensuring inherent on-time matching (±6%) and reduced output capacitor ripple current. |
| Sensorless current shaping | Eliminates external current-sense transformer or high-side shunt, simplifying PCB layout and improving efficiency by removing parasitic losses. |
| Inrush-safe current limiting | Prevents MOSFET conduction during cold-start; avoids reverse recovery stress in output rectifiers and eliminates need for snubber circuits. |
| FailSafe OVP with dual sensing | Independent VSENSE and HVSEN thresholds (6.45 V / 4.87 V) with latch-and-hold behavior protect against single-point voltage-sensing failures. |
| Adaptive phase management | PHB pin enables dynamic switching between two-phase (full load) and single-phase (light load) operation, improving efficiency below 30% load. |
Applications
| LCD/Plasma TV Power Supply | Computer Power Supply (ATX) |
|---|---|
|
Use Scenario: 400 VDC bulk supply generation for backlight inverters and main logic rails in 32–65 inch flat-panel TVs. IC Role / Device Role / Timing Role: Dual-phase TM PFC controller managing interleaved boost stages to meet IEC 61000-3-2 Class D harmonic limits. Use Value: Reduces bulk capacitor RMS current by ~30% vs. single-phase, enabling smaller 105°C electrolytics and lowering EMI filter size. |
Use Scenario: Active PFC front-end in 500–750 W ATX PSUs powering desktop PCs and workstations. IC Role / Device Role / Timing Role: Transition-mode controller regulating 400 VDC bus while maintaining >95% efficiency at 20% load via adaptive phase shedding. Use Value: Achieves 80 PLUS Gold efficiency certification through light-load optimization and zero-voltage switching at boundary condition. |
| Entry-Level Server PSU | Electronic Lighting Ballast |
|
Use Scenario: High-density 600 W server power supply operating continuously in 24/7 data center environments. IC Role / Device Role / Timing Role: Dual-channel PFC IC providing robust overvoltage, brownout, and thermal protection with FailSafe OVP redundancy. Use Value: Prevents catastrophic failure from HVSEN open-circuit or VSENSE resistor drift, extending mean time between failures (MTBF). |
Use Scenario: Digital ballast for HID lamps requiring stable 300–400 VDC bus with fast transient response to lamp ignition events. IC Role / Device Role / Timing Role: Fast-response TM PFC controller with 100 ns current-limit response time and 20 ms brownout filtering. Use Value: Maintains regulation during lamp arc instability without dropping out, avoiding re-ignition cycles and audible lamp buzz. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase transition-mode PFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28063DR | SOIC-16 pin-compatible; adds programmable soft-start and enhanced burst-mode control for lower no-load power. | Better suited for sub-1-W standby compliance; lacks UCC28060DG4's PHB-based adaptive phase management. | Select UCC28063DR when ultra-low no-load consumption (<300 mW) is mandatory; retain UCC28060DG4 for proven phase-shedding efficiency above 10% load. |
| ICE3PCS01G | Fixed-frequency CCM PFC controller; no Natural Interleaving; requires external current sense and zero-cross detection. | Higher EMI and bulk capacitor stress; simpler design but lower peak efficiency in 400–600 W range. | Choose ICE3PCS01G only if cost sensitivity outweighs ripple current reduction and light-load efficiency targets. |
Compared with UCC28060DG4, UCC28063DR improves no-load performance but sacrifices adaptive phase control, while ICE3PCS01G trades complexity for fixed-frequency predictability at the cost of higher RMS currents and reduced TM-specific efficiency gains.
Availability
UCC28060DG4 is available at Aetrix Electronics and suitable for LCD/Plasma TV power supplies, ATX computer PSUs, and entry-level server front-ends requiring stable component supply, long-term lifecycle support, and automotive-grade temperature resilience.
Supply support for UCC28060DG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.
The UCC28060DG4 belongs to TI's Natural Interleaving™ PFC controller family, engineered specifically for cost-sensitive, high-volume consumer and industrial AC-DC power supplies demanding high efficiency, low EMI, and robust system-level protection.
FAQ
What is the primary function of the PHB pin on the UCC28060DG4?
The PHB pin on the UCC28060DG4 controls phase B activation to enable adaptive two-phase or single-phase operation. When driven low or connected to AGND, it disables phase B and doubles phase A's on-time to maintain COMP voltage stability. Its threshold varies with VINAC range (e.g., 0.8–0.9 V low-line, 1.2–1.4 V high-line), allowing dynamic efficiency optimization across load conditions. This behavior is intrinsic to the UCC28060DG4's Natural Interleaving™ architecture and is not configurable via external registers.
How does the UCC28060DG4 implement FailSafe OVP, and why are two sense inputs required?
The UCC28060DG4 implements FailSafe OVP using two independent inputs - VSENSE (6.45 V rising threshold) and HVSEN (4.87 V rising threshold) - each with dedicated comparators and latch logic. If either input exceeds its threshold, PWM is immediately disabled and remains latched until reset. This dual-path design prevents catastrophic overvoltage caused by single-point failures such as open-circuit feedback resistors or shorted voltage dividers - a key reliability feature confirmed in the UCC28060DG4 datasheet Section 7.3.2.
What is the significance of the 100 ns current sense blanking time in the UCC28060DG4?
The UCC28060DG4 applies a fixed 100 ns blanking window after each GDA or GDB falling edge to ignore false current-sense signals caused by MOSFET-to-diode current transfer noise. During this interval, the CS comparator is disabled, preventing spurious overcurrent shutdowns during switching transitions. This timing is hard-coded in the UCC28060DG4 silicon and eliminates the need for external RC filters, simplifying design while maintaining cycle-by-cycle protection integrity at full switching frequencies.
Can the UCC28060DG4 operate with only one phase active, and how is that configured?
Yes, the UCC28060DG4 supports single-phase operation by pulling the PHB pin low (≤0.9 V at low line, ≤1.2 V at high line) or connecting it to AGND. In this mode, phase B is disabled and phase A's on-time doubles automatically to maintain output regulation. The UCC28060DG4 retains all protections (brownout, OVP, thermal shutdown) and continues using ZCDA for zero-cross detection. This configuration is explicitly documented in the UCC28060DG4 datasheet Figure 17 and Section 8.3.5.
What are the absolute maximum ratings for the ZCDA and ZCDB pins on the UCC28060DG4?
The UCC28060DG4 specifies absolute maximum ratings of –0.5 V to +4 V for ZCDA and ZCDB pins. Internally, these inputs are clamped between –0.2 V and +3.0 V, with ±3 mA clamp current limits. Exceeding the –0.5 V lower limit risks forward-biasing internal ESD diodes, while voltages above +4 V may damage input structures. These limits are defined in the Absolute Maximum Ratings table of the UCC28060DG4 datasheet (SLUS767E, p.3) and apply regardless of external series resistor value.
UCC28060DG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- Natural Interleaving™
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Mode:
- Discontinuous (Transition)
- Frequency - Switching:
- 500kHz
- Current - Startup:
- 200 µA
- Voltage - Supply:
- 8V ~ 21V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
UCC28060DG4 FAQ
1.How can I place an order for UCC28060DG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC28060DG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC28060DG4 reliable?
The price and inventory of UCC28060DG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC28060DG4 is usually 5 days.
3.What payment methods are accepted for UCC28060DG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC28060DG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC28060DG4?
UCC28060DG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC28060DG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC28060DG4?
For technical support, including UCC28060DG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC28060DG4 requirements.
6.How does Aetrix verify that UCC28060DG4 is sourced from the original manufacturer or authorized distributors?
All UCC28060DG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28060DG4 meets industry standards.
7.What is the process for return or replacement of UCC28060DG4?
All UCC28060DG4 units undergo pre-shipment inspection (PSI). If there is an issue with UCC28060DG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28060DG4 part is unused and in its original packaging.
Return procedure for UCC28060DG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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