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Texas Instruments UCC28061DG4
- Part No.:
- UCC28061DG4
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
UCC28061DG4.pdf
- Description:
- IC PFC CTRL TRANS 500KHZ 16SOIC
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
UCC28061DG4 from Texas Instruments is a natural interleaving transition-mode power factor correction (PFC) controller designed for 100–800 W AC-DC front-end stages. It integrates dual-channel gate drivers (1 A source / 1.8 A sink), sensorless current shaping, and FailSafe OVP with dual-path HVSEN/VSENSE monitoring. It operates across 85–265 VAC input and delivers improved audible noise immunity in LCD/Plasma TVs and gaming power supplies.
For engineers reviewing the UCC28061DG4 datasheet, UCC28061DG4 pinout, UCC28061DG4 application, or UCC28061DG4 equivalent, key selection criteria include its two-phase interleaved TM operation, ±25 mA continuous gate drive capability, 1.7–2.5 µs minimum switching period, brownout detection with 440 ms filter delay, and SOIC-16 thermal rating of 890 mW at +25°C.
Technical Context
The UCC28061DG4 implements Natural Interleaving™-a master-master dual-channel architecture where both phases operate synchronously at identical frequency without slave dependency, enabling inherent channel matching and faster transient response. Its transconductance error amplifier (96 µS typ) regulates output voltage via VSENSE feedback against a 6.00 V reference, with COMP output directly modulating on-time proportional to (VCOMP – 125 mV).
Zero-current detection on ZCDA/ZCDB inputs (falling threshold 0.8–1.2 V, rising 1.5–1.88 V) triggers gate drive edges with 45–100 ns delay; PHB pin enables phase management by disabling Channel B and doubling Channel A on-time. FailSafe OVP uses independent thresholds on HVSEN (4.87 V rising) and VSENSE (6.45 V rising) to prevent catastrophic overvoltage from single-point failures.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC operating range | 14–21 V - powers internal circuitry and gate drivers; clamped at 24 V typical to prevent damage |
| Gate drive output | 1 A source / 1.8 A sink - drives MOSFET gates directly without external buffers in most designs |
| Minimum switching period | 1.7–2.5 µs - sets maximum practical switching frequency (~588 kHz) and impacts EMI filter sizing |
| VSENSE regulation voltage | 5.82–6.18 V - defines precise 400 VDC output setpoint when used with standard resistor divider |
| Brownout filter delay | 340–540 ms - prevents nuisance shutdown during brief AC sags while ensuring reliable low-line protection |
| Thermal shutdown | +160°C activation / +140°C restart - protects IC during sustained overload or poor heatsinking |
| ZCD falling threshold | 0.8–1.2 V - detects inductor current zero-crossing with low propagation delay for accurate TM timing |
Pinout & Package
UCC28061DG4 is housed in a 16-pin SOIC (D) package with exposed pad not present; thermal resistance θJA = 140°C/W. Pin functions are validated per TI SLUS837A datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ZCDB (Pin 1) | Zero-current detection input B | Detects falling edge of inductor current in Phase B; must drop below ~1 V to trigger GDB rise |
| VREF (Pin 15) | 6 V precision reference output | Provides stable bias for external circuits (≤2 mA load); shuts off during UVLO to reduce quiescent current |
| GDA (Pin 14) | Phase A gate driver output | Drives high-side boost MOSFET gate; 1 A source / 1.8 A sink capability supports fast turn-on/turn-off |
| PGND (Pin 13) | Power ground return | Separate low-impedance path for gate driver return current to isolate analog AGND from switching noise |
| VCC (Pin 12) | Bias supply input | Accepts regulated 14–21 V; requires 0.1 µF ceramic bypass to PGND placed adjacent to pin |
| GDB (Pin 11) | Phase B gate driver output | Drives second boost MOSFET; synchronized but independent of GDA via Natural Interleaving™ |
| CS (Pin 10) | Cycle-by-cycle current sense input | Monitors negative-going voltage across sense resistor; trips at –0.20 V (typ) to disable both GD outputs |
| PWMCNTL (Pin 9) | Open-drain PWM enable logic output | Signals downstream converter readiness: low when HVSEN is in valid range and ZCD inputs active |
| ZCDA (Pin 16) | Zero-current detection input A | Triggers GDA edge on inductor current zero crossing; clamped between 0 V and 3 V for robustness |
| VSENSE (Pin 2) | Output voltage feedback input | Compares divided DC bus voltage against 6 V internal reference; pulled low disables gate drivers |
| TSET (Pin 3) | On-time programming input | Resistor to AGND sets KT factor (4.0 µs/V typ) and minimum period; adjusts gain for line/load compensation |
| PHB (Pin 4) | Phase B enable control | High = two-phase operation; low = single-phase with doubled Channel A on-time for seamless transition |
| COMP (Pin 5) | Error amplifier output | Transconductance output (96 µS) controlling on-time; clamped high/low to ensure safe soft-start recovery |
| AGND (Pin 6) | Analog ground reference | Star point for compensation networks, VREF bypass, and signal returns; tied to PGND at single point |
| VINAC (Pin 7) | AC input voltage sense | Monitors rectified mains for brownout detection; 1.39 V (typ) falling threshold with 440 ms hysteresis filter |
| HVSEN (Pin 8) | High-voltage output sense | Redundant OVP path; 4.87 V rising threshold enables power-good signaling to downstream converters |
Key Features
| Feature | Design Value |
|---|---|
| Natural Interleaving™ architecture | Master-master dual-phase synchronization eliminates slave dependency, improving channel matching and dynamic response |
| Sensorless current shaping | Eliminates current-sense transformer or Hall-effect sensor, reducing BOM cost and board area in PFC stage |
| FailSafe OVP with dual sensing | Independent HVSEN and VSENSE overvoltage paths prevent single-failure overvoltage events on 400 VDC bus |
| Inrush-safe current limiting | Prevents MOSFET conduction during startup and eliminates reverse-recovery stress on output rectifiers |
| Soft start on overvoltage | Forces COMP discharge below 0.5 V before resuming operation, ensuring controlled restart after OVP fault |
| Phase management via PHB pin | Enables seamless transition between two-phase and single-phase operation under light-load conditions for efficiency optimization |
Applications
| LCD/Plasma TV Power Supplies | Gaming Console AC-DC Adapters |
|---|---|
|
Use Scenario: 300–600 W PFC front-end for flat-panel display power systems operating from universal AC input. IC Role / Device Role / Timing Role: Dual-phase TM PFC controller regulating 400 VDC bus while suppressing audible noise from inductor vibration. Use Value: Natural Interleaving reduces input capacitor ripple current by >50% versus single-phase CCM, enabling smaller bulk capacitors and lower EMI filter cost. |
Use Scenario: High-efficiency, low-noise AC-DC adapter for next-generation gaming consoles requiring tight hold-up time and thermal margin. IC Role / Device Role / Timing Role: Transition-mode PFC controller delivering >95% efficiency at 230 VAC full load with integrated gate drivers and system-level protection. Use Value: FailSafe OVP and brownout detection ensure robust operation during grid fluctuations common in consumer environments. |
| Home Audio Amplifier Power Stages | Digital Set-Top Box Power Modules |
|
Use Scenario: High-fidelity audio system power supply where low EMI and zero audible coil whine are mandatory design requirements. IC Role / Device Role / Timing Role: Two-phase interleaved PFC controller minimizing differential-mode noise and magnetic component vibration at line frequency harmonics. Use Value: Improved light-load efficiency and soft-start on overvoltage prevent pop/click artifacts during power cycling. |
Use Scenario: Compact, cost-sensitive 120–200 W power module for cable/satellite STBs with strict energy efficiency mandates (e.g., ENERGY STAR). IC Role / Device Role / Timing Role: Integrated PFC controller with sensorless current shaping and inrush-safe limiting to meet Class D standby power limits. Use Value: Eliminates need for snubber networks on low-cost diodes, reducing component count and assembly cost in high-volume production. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transition-mode PFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28063DR | SOIC-16 package with same pinout; enhanced EMI performance via optimized gate drive slew rate control | Better suited for ultra-low EMI designs (e.g., medical-grade adapters) where radiated emissions compliance is critical | Select UCC28063DR when EMI filter size reduction or CISPR-22 Class B compliance is prioritized over cost |
| ICE3PCS01G | Fixed-frequency CCM PFC controller with integrated 650 V MOSFET; no interleaving capability; different protection scheme | Targeted at lower-power (<300 W), cost-sensitive applications where simplicity and integration outweigh TM efficiency benefits | Choose ICE3PCS01G only for non-interleaved, fixed-frequency designs accepting higher conduction losses and larger input filters |
Compared with UCC28061DG4, UCC28063DR offers identical functionality with refined EMI behavior, while ICE3PCS01G trades interleaving and TM efficiency for monolithic integration and lower BOM count-making it unsuitable as a drop-in replacement but viable for simplified CCM implementations.
Availability
UCC28061DG4 is available at Aetrix Electronics and suitable for LCD/Plasma TV power supplies, gaming console adapters, and home audio amplifier front-ends requiring stable component supply and long-term industrial availability.
Supply support for UCC28061DG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 50 years of innovation in power conversion ICs.
The UCC28061DG4 belongs to TI's Natural Interleaving™ PFC controller product line, engineered specifically to extend transition-mode efficiency and low-noise operation into 600–800 W consumer power applications.
FAQ
What is the primary function of the PHB pin on the UCC28061DG4?
The PHB pin on the UCC28061DG4 controls Phase B operation: when pulled high, both channels operate in Natural Interleaving™ two-phase mode; when pulled low, Channel B is disabled and Channel A's on-time doubles to maintain output regulation. This enables seamless light-load efficiency optimization without external sequencing logic. The UCC28061DG4 uses this pin to dynamically manage phase count based on load demand while preserving stability.
Does the UCC28061DG4 support direct connection to 400 VDC bus for HVSEN monitoring?
No, the UCC28061DG4 does not support direct 400 VDC connection to HVSEN. The HVSEN pin has an absolute maximum rating of 4.5 V and requires a resistive divider to scale the 400 VDC bus down to 2.5 V (typical power-good threshold) with appropriate impedance for hysteresis. The UCC28061DG4 relies on this scaled signal for FailSafe OVP and downstream converter enable signaling-not raw high-voltage sensing.
How does the UCC28061DG4 achieve audible noise immunity in PFC stages?
The UCC28061DG4 achieves audible noise immunity through Natural Interleaving™-which spreads switching energy across two phases-and optimized zero-current detection with tight threshold tolerances (±0.2 V). This minimizes inductor core vibration at 100/120 Hz harmonics. The UCC28061DG4 also incorporates soft-start on overvoltage and inrush-safe current limiting to suppress mechanical stress during transients, directly addressing coil whine in consumer displays.
What is the purpose of the TSET pin on the UCC28061DG4, and how is it configured?
The TSET pin on the UCC28061DG4 programs the on-time scaling factor (KT = 4.0 µs/V typ) and minimum switching period via an external resistor to AGND. A 133 kΩ resistor yields 2.2 µs minimum period; values from 66.5 kΩ to 400 kΩ adjust timing across operating conditions. The UCC28061DG4 uses this pin to maintain consistent TM behavior across line/load variations without requiring loop compensation changes.
Can the UCC28061DG4 operate in single-phase mode, and how is that enabled?
Yes, the UCC28061DG4 supports single-phase operation by pulling the PHB pin low, which disables Channel B and doubles Channel A's on-time to maintain power delivery. This mode retains all protections and regulation accuracy while reducing switching losses at light loads. The UCC28061DG4 transitions seamlessly between modes without external controllers-enabling adaptive efficiency in variable-load applications like STBs and audio amplifiers.
UCC28061DG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- Natural Interleaving™
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Mode:
- Discontinuous (Transition)
- Frequency - Switching:
- 500kHz
- Current - Startup:
- 100 µA
- Voltage - Supply:
- 14V ~ 21V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
UCC28061DG4 FAQ
1.How can I place an order for UCC28061DG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC28061DG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC28061DG4 reliable?
The price and inventory of UCC28061DG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC28061DG4 is usually 5 days.
3.What payment methods are accepted for UCC28061DG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC28061DG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC28061DG4?
UCC28061DG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC28061DG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC28061DG4?
For technical support, including UCC28061DG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC28061DG4 requirements.
6.How does Aetrix verify that UCC28061DG4 is sourced from the original manufacturer or authorized distributors?
All UCC28061DG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28061DG4 meets industry standards.
7.What is the process for return or replacement of UCC28061DG4?
All UCC28061DG4 units undergo pre-shipment inspection (PSI). If there is an issue with UCC28061DG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28061DG4 part is unused and in its original packaging.
Return procedure for UCC28061DG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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