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Texas Instruments UCC28061DRG4
- Part No.:
- UCC28061DRG4
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
UCC28061DRG4.pdf
- Description:
- IC PFC CTRL TRANS 500KHZ 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,252
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Product details
Overview
UCC28061DRG4 from Texas Instruments is a natural interleaving transition-mode (TM) power factor correction (PFC) controller for two-phase boost converters. It delivers 1-A source/1.8-A sink gate drive, supports 100–800 W systems, operates from –40°C to +125°C, and features integrated brownout, FailSafe OVP, and phase-fail detection. It enables high-efficiency, low-audible-noise PFC in LCD/Plasma TVs and gaming power supplies.
For engineers reviewing the UCC28061DRG4 datasheet, UCC28061DRG4 pinout, UCC28061DRG4 application, or UCC28061DRG4 equivalent, key selection criteria include its dual-channel TM interleaving architecture, 16-pin SOIC package, 12.6 V UVLO turn-on threshold, ±25 mA gate drive capability, and HVSEN/VSENSE dual overvoltage monitoring for system-level safety compliance.
Technical Context
The UCC28061DRG4 implements a master–master Natural Interleaving™ architecture-both channels operate autonomously at synchronized frequency without slave dependency-ensuring inherent channel matching and fast transient response. Its sensorless current shaping eliminates need for secondary current sensing, reducing board complexity.
It integrates dual zero-current detection (ZCDA/ZCDB), programmable on-time via TSET resistor, PHB-controlled phase management, and FailSafe OVP using redundant HVSEN and VSENSE inputs. The error amplifier features 96 µS transconductance and 125 mV internal offset for precise COMP-to-on-time mapping.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 14 V to 21 V - powers all internal circuitry; clamped at 24 V typical to prevent damage |
| UVLO Turn-on Threshold | 12.6 V typical - ensures reliable startup after input stabilization |
| Gate Drive Strength | 1 A source / 1.8 A sink - directly drives MOSFET gates without external buffers in most 600 W designs |
| VSENSE Regulation Voltage | 6.00 V ±0.15 V - sets output voltage via external divider; enables 380–400 VDC PFC outputs |
| ZCD Thresholds | Falling: 1.0 V typ; Rising: 1.68 V typ - detects inductor zero-crossing with noise immunity for stable TM operation |
| HVSEN OVP Threshold | 4.87 V typ - triggers shutdown if bulk capacitor exceeds safe level, independent of VSENSE path |
| TSET On-time Scaling | 4.0 µs/V typ - linearly programs PWM on-time vs COMP voltage; RTSET = 133 kΩ yields 2.2 µs min period |
Pinout & Package
UCC28061DRG4 is housed in a 16-pin SOIC (D) package with standard 1.27 mm pitch, JEDEC MS-012AC compliant, suitable for automated assembly and thermal derating up to 890 mW at 25°C ambient.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ZCDB (1) | Zero-current detect B input | Monitors phase B inductor zero-crossing; falling edge below 1.0 V triggers GDB rise |
| VREF (15) | 6 V reference output | Stable 6 V bias for external circuits; shuts down during UVLO or disable to reduce quiescent current |
| GDA (14) | Phase A gate driver output | 1.8 A sink / 1 A source drive; connects directly to MOSFET gate with optional 5–10 Ω series damping |
| PGND (13) | Power ground return | Separate low-impedance path for gate driver return; must be short-traced to AGND at single point |
| VCC (12) | Bias supply input | Accepts regulated 14–21 V; requires 0.1 µF ceramic bypass to PGND for noise immunity |
| GDB (11) | Phase B gate driver output | Matches GDA specs; disabled when PHB < 0.8 V to enable single-phase operation |
| CS (10) | Current sense input | Cycle-by-cycle protection: trips at –0.20 V rising threshold; blanked 100 ns post-GD fall |
| PWMCNTL (9) | Open-drain PWM enable | Low when HVSEN in valid range AND ZCDA/ZCDB switching correctly; used for downstream converter enable |
| ZCDA (16) | Zero-current detect A input | Same function as ZCDB; rising edge >1.68 V arms logic for next falling edge |
| VSENSE (2) | Output voltage feedback | 6 V regulation target; pulled low by open-drain disable signal or internal open-loop protection |
| TSET (3) | On-time programming input | Resistor-to-AGND sets KT factor; 133 kΩ yields 4.0 µs/V scaling and 2.2 µs min period |
| PHB (4) | Phase B enable control | Logic input: <0.8 V disables phase B; >0.9 V enables two-phase interleaving |
| COMP (5) | Error amplifier output | Transconductance amplifier output; on-time ∝ (VCOMP – 125 mV); pulled low during soft-start |
| AGND (6) | Analog ground reference | Return for compensation network, VREF bypass, and analog signal paths; isolated from PGND |
| VINAC (7) | AC input voltage sense | Detects brownout: falls below 1.39 V for >440 ms → disables both GD outputs |
| HVSEN (8) | High-voltage output sense | Redundant OVP path; 4.87 V threshold provides fail-safe shutdown if VSENSE fails open |
Key Features
| Feature | Design Value |
|---|---|
| Natural Interleaving™ architecture | Master–master dual-channel synchronization eliminates phase skew and improves ripple cancellation without clock distribution |
| Sensorless current shaping | Eliminates secondary current sense transformer or shunt, reducing BOM cost and layout area while improving efficiency |
| FailSafe OVP with dual sensing | Independent HVSEN and VSENSE inputs ensure shutdown even if one path fails short or open-critical for UL/IEC 62368-1 compliance |
| Inrush-safe current limiting | Prevents MOSFET conduction during startup and eliminates reverse recovery stress in output rectifiers |
| Phase management via PHB pin | Enables dynamic transition between two-phase (full load) and single-phase (light load) modes to improve light-load efficiency |
Applications
| LCD/Plasma/DLP™ TV Power Supplies | Gaming Console AC-DC Adapters |
|---|---|
Use Scenario: 300–600 W front-end PFC stage feeding resonant LLC or PWM DC-DC converter in flat-panel display power systems. IC Role / Device Role / Timing Role: Dual-phase TM PFC controller managing interleaved boost stages to meet EN61000-3-2 Class C harmonic limits and reduce audible coil whine. Use Value: Natural Interleaving reduces input filter and bulk capacitor ripple current by >40% versus single-phase TM, enabling smaller EMI filters and 25% smaller 400 VDC bulk capacitors. | Use Scenario: High-density 400–500 W adapter for next-gen gaming consoles requiring tight hold-up time and low standby power. IC Role / Device Role / Timing Role: Transition-mode PFC controller delivering high efficiency (>95%) across 20–100% load while maintaining low THD under dynamic load steps. Use Value: Integrated brownout detection and FailSafe OVP satisfy IEC 62368-1 fault tolerance requirements; PHB-based phase shedding improves 10%–20% load efficiency by >3 percentage points. |
| Home Audio System Power Modules | Digital Set-Top Box (STB) Power Supplies |
Use Scenario: Premium AV receiver or soundbar with multi-rail outputs (±15 V, 5 V, 12 V) fed from high-efficiency PFC + isolation stage. IC Role / Device Role / Timing Role: Two-phase TM PFC controller providing low-noise, high-power-factor front-end with minimal acoustic emission during quiet listening conditions. Use Value: Improved audible noise immunity prevents transformer/inductor buzz at line frequency harmonics; soft-start on overvoltage avoids output overshoot during hot-plug events. | Use Scenario: Compact 100–150 W STB power supply operating from universal 85–265 VAC input with strict no-load power (<0.5 W) and harmonic compliance. IC Role / Device Role / Timing Role: Low-power TM PFC controller enabling single-stage design with integrated protections and phase management for burst-mode operation. Use Value: Inrush-safe limiting and 100 µA standby VCC current support Energy Star Tier 2 compliance; HVSEN-based power-good signal enables precise downstream converter sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transition-mode PFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28063DR | Same pinout and core functionality; adds programmable soft-start delay and enhanced ZCD filtering for higher EMI immunity | Better suited for high-noise industrial environments where ZCD false triggering is observed | Select UCC28063DR when ZCD robustness under noisy mains or high dv/dt is critical; otherwise UCC28061DRG4 offers proven cost/performance balance |
| L6562A | Single-phase TM PFC controller; no interleaving, no PHB, no HVSEN; 8-pin SOIC package | Limited to ≤300 W; requires external OVP and brownout circuitry; no phase management | Choose L6562A only for cost-sensitive, lower-power (<250 W), non-interleaved designs where dual-phase ripple reduction is unnecessary |
Compared with UCC28063DR and L6562A, the UCC28061DRG4 uniquely balances dual-phase interleaving, FailSafe OVP redundancy, and PHB-based light-load optimization-making it the optimal choice for 300–600 W consumer electronics PFC where reliability, noise, and efficiency must coexist.
Availability
UCC28061DRG4 is available at Aetrix Electronics and suitable for LCD/Plasma TV power supplies, gaming console adapters, home audio system modules, and digital set-top box power supplies requiring stable component supply and long-term industrial lifecycle support.
Supply support for UCC28061DRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in power conversion and energy-efficient system design.
The UCC28061DRG4 belongs to TI's high-performance PFC controller product line, engineered specifically for consumer-grade AC-DC front-ends demanding low audible noise, high reliability, and seamless integration with downstream DC-DC stages.
FAQ
What is the primary function of the UCC28061DRG4 in a power supply design?
The UCC28061DRG4 serves as a dual-channel transition-mode power factor correction controller that manages interleaved boost converters to achieve high power factor, low THD, and reduced EMI. It regulates output voltage via VSENSE feedback, senses zero-current crossing for timing, drives external MOSFETs through GDA/GDB outputs, and provides comprehensive protection including brownout, overvoltage, and thermal shutdown-all within a single 16-pin SOIC package. Its Natural Interleaving™ architecture ensures balanced phase operation without master-slave dependencies.
How does the FailSafe OVP feature work in the UCC28061DRG4?
The UCC28061DRG4 implements FailSafe OVP using two independent sensing paths: VSENSE and HVSEN. If either input exceeds its respective overvoltage threshold-6.45 V for VSENSE or 4.87 V for HVSEN-the PWM is immediately disabled. This dual-path design ensures protection remains active even if one sensing node fails short or open, meeting stringent safety standards like IEC 62368-1. The HVSEN path also provides a power-good signal via PWMCNTL, enabling controlled downstream converter startup.
Can the UCC28061DRG4 operate in single-phase mode, and how is it configured?
Yes, the UCC28061DRG4 supports dynamic phase management. When the PHB pin voltage drops below 0.8 V, phase B is disabled and phase A's on-time doubles to maintain output regulation. This allows seamless transition from two-phase (full load) to single-phase (light load) operation, improving light-load efficiency. To force single-phase mode, tie PHB to AGND; for full two-phase operation, connect PHB to VREF. The PHB threshold has 0.2 V hysteresis to prevent oscillation near the transition point.
What are the absolute maximum ratings for the VCC and CS pins of the UCC28061DRG4?
The UCC28061DRG4 specifies an absolute maximum VCC voltage of +21 V and a continuous VCC input current limit of 20 mA. Exceeding these may cause permanent damage. For the CS pin, the absolute maximum input voltage is +7 V, but normal operation uses negative-going signals; the CS rising overcurrent threshold is –0.20 V typical, and the pin is blanked for 100 ns after each gate drive fall to reject noise. Input current beyond ±5 mA is not recommended per datasheet guidance.
Is the UCC28061DRG4 RoHS-compliant and qualified for automotive applications?
The UCC28061DRG4 is RoHS-compliant and meets JEDEC J-STD-020 moisture sensitivity level 3. However, it is specified for industrial/consumer temperature range (–40°C to +125°C) and is not AEC-Q200 qualified. Texas Instruments positions this device for high-reliability consumer applications-including TVs, gaming adapters, and audio systems-but does not certify it for automotive underhood use. For automotive-grade PFC, TI recommends the UCC28064A or UCC28070 families with extended qualification and ASIL-ready features.
UCC28061DRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- Natural Interleaving™
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Mode:
- Discontinuous (Transition)
- Frequency - Switching:
- 500kHz
- Current - Startup:
- 100 µA
- Voltage - Supply:
- 14V ~ 21V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
UCC28061DRG4 FAQ
1.How can I place an order for UCC28061DRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC28061DRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC28061DRG4 reliable?
The price and inventory of UCC28061DRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC28061DRG4 is usually 5 days.
3.What payment methods are accepted for UCC28061DRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC28061DRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC28061DRG4?
UCC28061DRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC28061DRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC28061DRG4?
For technical support, including UCC28061DRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC28061DRG4 requirements.
6.How does Aetrix verify that UCC28061DRG4 is sourced from the original manufacturer or authorized distributors?
All UCC28061DRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28061DRG4 meets industry standards.
7.What is the process for return or replacement of UCC28061DRG4?
All UCC28061DRG4 units undergo pre-shipment inspection (PSI). If there is an issue with UCC28061DRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28061DRG4 part is unused and in its original packaging.
Return procedure for UCC28061DRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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