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Texas Instruments UCC28061QDRQ1
- Part No.:
- UCC28061QDRQ1
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
UCC28061QDRQ1.pdf
- Description:
- IC PFC CTR TRANS 45KHZ 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,820
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Product details
Overview
UCC28061QDRQ1 from Texas Instruments is an AEC-Q100 Grade 1 qualified natural interleaving transition-mode (TM) PFC controller for automotive and industrial 100–800 W power supplies. It features dual-channel gate drivers (1-A source/1.8-A sink), integrated brownout detection, fail-safe OVP with dual-path HVSEN/VSENSE monitoring, and sensorless current shaping. It enables high-efficiency, low-audible-noise PFC in e-bike chargers and on-board chargers.
For engineers reviewing the UCC28061QDRQ1 datasheet, UCC28061QDRQ1 pinout, UCC28061QDRQ1 application, or UCC28061QDRQ1 equivalent, key selection criteria include its two-phase TM interleaving architecture, automotive-grade thermal shutdown (160°C), ±25 mA continuous gate drive capability, and dual OVP fault tolerance-critical for safety-compliant 400 VDC output systems.
Technical Context
The UCC28061QDRQ1 implements Natural Interleaving™-a master-master two-phase TM control scheme where both channels self-synchronize without a slave, delivering inherent phase matching and fast transient response. Its transconductance error amplifier (96 μS typ) regulates output voltage via VSENSE feedback referenced to 6.0 V internal VREF.
Phase management is dynamically controlled via PHB input, enabling seamless single-/two-phase operation based on line voltage and load. FailSafe OVP uses independent thresholds on HVSEN (4.87 V rising) and VSENSE (6.45 V rising), with separate hysteresis and fault latching to prevent catastrophic overvoltage from sensing failures.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC operating range | 14 V to 21 V - powers all internal circuits including 1-A/1.8-A gate drivers; clamped at 24 V to prevent damage |
| Gate drive output | 1-A source / 1.8-A sink - drives MOSFET gates directly without external buffers in most 600-V designs |
| VSENSE regulation voltage | 6.00 V ±0.18 V - sets nominal 400 VDC output via resistor divider; enables precise output voltage programming |
| HVSEN OVP threshold | 4.87 V (rising) - triggers immediate PWM shutdown if high-side sense fails, providing redundant protection |
| Thermal shutdown | +160°C (rising), +140°C (falling) - ensures safe operation in under-hood automotive environments |
| ZCDA/ZCDB thresholds | Falling: 1.0 V typ; Rising: 1.68 V typ - enables accurate zero-current detection for TM boundary conduction |
| PHB enable threshold | 0.8 V (falling) to disable Phase B; 1.0 V (rising) to re-enable - supports adaptive light-load efficiency optimization |
Pinout & Package
UCC28061QDRQ1 is housed in a 16-pin SOIC (D) package with exposed pad thermal enhancement, rated for –40°C to +125°C ambient operation and qualified per AEC-Q100 Grade 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ZCDB (1) | Zero-current detect input B | Detects inductor current zero-crossing for Phase B; falling edge below ~1.0 V triggers GDB rise |
| AGND (6) | Analog ground reference | Return for error amp, compensation network, and analog signal paths; must be isolated from PGND except at single point |
| COMP (5) | Error amplifier output | Transconductance output (96 μS); gate on-time ∝ (VCOMP – 125 mV); soft-start pulls low to ensure safe restart |
| CS (10) | Cycle-by-cycle current sense | Overcurrent protection at –200 mV rising threshold; blanked for 100 ns after GD edge to reject diode-recovery noise |
| GDA (14) | Phase A gate driver output | 1-A source / 1.8-A sink; drives boost MOSFET gate; requires short trace or series damping resistor if >12.6 mm |
| GDB (11) | Phase B gate driver output | Identical specs to GDA; enables true interleaved two-phase operation with matched timing and ripple cancellation |
| VSENSE (2) | Output voltage feedback | 6.0 V regulation reference; open-loop protection pulls it low if disconnected, disabling outputs and reducing IVCC |
| HVSEN (8) | Redundant high-voltage OVP sense | Independent OVP path (4.87 V rising); also provides power-good signal to downstream converters when within 2.5 V window |
| PHB (4) | Phase B enable control | Dynamic phase shedding: pull <0.8 V to disable Phase B and double Phase A on-time, maintaining COMP stability |
| TSET (3) | PWM on-time programming | Resistor-to-AGND sets on-time factor KTL (4.0 μs/V typ) and minimum switching period (2.2 μs typ) |
| VINAC (7) | AC input voltage monitor | Brownout detection at 1.39 V falling; 440 ms filter prevents false trips during line dips |
| VCC (12) | Bias supply input | 14–21 V regulated input; powers all logic and drivers; internal clamp protects against overvoltage |
| PWMCNTL (9) | Open-drain PWM enable output | Low when HVSEN is valid AND ZCDA/ZCDB are toggling correctly; used for system-level sequencing and fault reporting |
| VREF (15) | 6.0 V precision reference | Stable 6 V output (±10 mV), max 2 mA load; turns off during UVLO/VSENSE disable to reduce quiescent current |
| PGND (13) | Power ground return | Return path for gate drivers and high-current switching nodes; must be short-traced to AGND at single point |
| ZCDA (16) | Zero-current detect input A | Symmetric to ZCDB; falling edge initiates GDA rise; clamped 0–3 V to protect against inductive kickback |
Key Features
| Feature | Design Value |
|---|---|
| Natural Interleaving™ architecture | Two master-phase TM control eliminates slave synchronization delay, enabling inherently matched timing and reduced output capacitor ripple |
| FailSafe OVP with dual sensing | Independent HVSEN and VSENSE OVP paths prevent single-point failure from causing overvoltage; each with dedicated thresholds and hysteresis |
| Soft-start on overvoltage | Automatic recovery after OVP event: COMP is held low until discharged below 0.5 V, ensuring controlled restart with minimal inrush |
| Inrush-safe current limiting | Prevents MOSFET conduction during startup by holding GD outputs low until VINAC exceeds brownout threshold and CS settles |
| Integrated brownout detection | 440 ms filtered VINAC monitoring at 1.39 V threshold ensures stable operation during AC line sags without false shutdowns |
Applications
| On-Board EV Charger | E-Bike Battery Charger |
|---|---|
Use Scenario: 3.3 kW bidirectional OBC with 400 VDC intermediate bus and active PFC front-end. IC Role / Device Role / Timing Role: Dual-phase TM PFC controller managing interleaved boost stages to meet CISPR-25 Class 5 EMI limits and IEC 61000-3-2 harmonic standards. Use Value: Natural Interleaving reduces bulk capacitor RMS current by >30%, enabling smaller 105°C-rated electrolytics and extending lifetime in under-hood thermal environments. | Use Scenario: 350 W portable e-bike charger with universal AC input (85–265 VAC) and 54.6 V battery output. IC Role / Device Role / Timing Role: Transition-mode PFC controller regulating 400 VDC bus while dynamically shedding Phase B below 20% load to maintain >92% efficiency at 10% load. Use Value: PHB-controlled phase management improves light-load efficiency by 4.2% versus fixed two-phase operation, meeting EU CoC Tier 2 requirements. |
| Automotive Lighting Power Supply | Industrial Motor Drive Front-End |
Use Scenario: 200 W LED headlamp driver requiring flicker-free operation and AEC-Q100 compliance. IC Role / Device Role / Timing Role: Automotive-grade PFC controller supplying clean 400 VDC bus to downstream LLC resonant converter, immune to engine cranking dips. Use Value: Integrated brownout (1.39 V VINAC threshold) and 440 ms filtering sustain operation during 6 V cold-crank events, preventing headlamp dropout. | Use Scenario: 750 W servo drive with regenerative braking and strict THD limits (<5%) across 3-phase input. IC Role / Device Role / Timing Role: High-power PFC controller implementing sensorless current shaping to eliminate current-sense resistor drift errors in harsh factory environments. Use Value: Sensorless shaping removes gain drift from temperature and aging, maintaining <3.5% THD over –25°C to +70°C ambient without recalibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28063QDRQ1 | Single-phase TM PFC controller; no interleaving; lower gate drive (0.5-A source/1-A sink); no PHB pin | Suitable for cost-sensitive ≤300 W designs where ripple cancellation and phase management are unnecessary | Select when system power ≤300 W and automotive qualification is required but dual-phase complexity is not justified |
| L6564HTR | Non-automotive TM PFC controller; no AEC-Q100 qualification; no HVSEN; only VSENSE-based OVP; 125°C max junction | Targeted at industrial/commercial 100–600 W supplies without automotive reliability or dual-OVP requirements | Choose for non-automotive applications needing proven TM performance but without fail-safe OVP or Grade 1 thermal rating |
Compared with UCC28061QDRQ1, UCC28063QDRQ1 lacks interleaving and phase management but offers lower BOM cost for simpler designs, while L6564HTR provides mature TM control without automotive qualification or dual-path OVP-making UCC28061QDRQ1 the only option meeting full AEC-Q100 Grade 1, Natural Interleaving, and FailSafe OVP requirements.
Availability
UCC28061QDRQ1 is available at Aetrix Electronics and suitable for automotive on-board chargers, e-bike battery systems, and industrial motor drive front-ends requiring stable component supply, AEC-Q100 compliance, and high-reliability PFC control.
Supply support for UCC28061QDRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with deep expertise in automotive-grade power conversion solutions.
The UCC28061QDRQ1 belongs to TI's automotive PFC controller product line, designed specifically for high-efficiency, low-noise, safety-critical AC-DC front-ends in electric mobility and under-hood electronics.
FAQ
What is the purpose of the PHB pin on the UCC28061QDRQ1?
The PHB pin on the UCC28061QDRQ1 controls Phase B operation: pulling it below 0.8 V disables Phase B and doubles Phase A on-time to maintain regulation, while raising it above 1.0 V re-enables two-phase interleaving. This dynamic phase management improves light-load efficiency and reduces audible noise in automotive and e-bike applications. The UCC28061QDRQ1 uses this feature to meet EU CoC Tier 2 requirements without external controllers.
How does the FailSafe OVP function work in the UCC28061QDRQ1?
The UCC28061QDRQ1 implements FailSafe OVP using two independent sensing paths: VSENSE (6.45 V rising threshold) and HVSEN (4.87 V rising threshold). Either path triggering causes immediate PWM shutdown and latches the fault until reset. This dual-path architecture prevents catastrophic overvoltage from single-component failures like open-divider resistors or PCB trace opens. The UCC28061QDRQ1 is the only AEC-Q100 Grade 1 PFC controller with this redundancy.
What is the recommended layout practice for AGND and PGND on the UCC28061QDRQ1?
For the UCC28061QDRQ1, AGND and PGND must be connected at a single point near the IC to prevent high-current switching noise from coupling into analog circuits. AGND carries error amplifier, compensation, and reference currents; PGND returns gate driver and power FET currents. Separating these planes except at one star point minimizes COMP voltage disturbance and improves regulation accuracy. This layout is critical for achieving <±1% output voltage stability in the UCC28061QDRQ1.
Can the UCC28061QDRQ1 operate in single-phase mode, and how is it configured?
Yes, the UCC28061QDRQ1 supports single-phase operation by pulling the PHB pin low (<0.8 V) or connecting it to AGND. In this mode, Phase A on-time doubles automatically to maintain output regulation, and GDB remains inactive. The UCC28061QDRQ1 retains full protection features-including brownout, OVP, and thermal shutdown-in single-phase mode, making it suitable for lower-power automotive subsystems where space or cost constraints limit two-phase implementation.
What is the role of the TSET pin in configuring the UCC28061QDRQ1's switching behavior?
The TSET pin on the UCC28061QDRQ1 sets the on-time factor (KTL = 4.0 μs/V typ) and minimum switching period (2.2 μs typ) via an external resistor to AGND. A 133 kΩ resistor yields nominal timing; increasing resistance extends on-time and reduces frequency, allowing optimization for EMI or efficiency trade-offs. This direct analog programming avoids digital configuration overhead and ensures deterministic timing in the UCC28061QDRQ1's automotive-grade operation.
UCC28061QDRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- Natural Interleaving™
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Mode:
- Discontinuous (Transition)
- Frequency - Switching:
- 45kHz
- Current - Startup:
- 100 µA
- Voltage - Supply:
- 14V ~ 21V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
UCC28061QDRQ1 FAQ
1.How can I place an order for UCC28061QDRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC28061QDRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC28061QDRQ1 reliable?
The price and inventory of UCC28061QDRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC28061QDRQ1 is usually 5 days.
3.What payment methods are accepted for UCC28061QDRQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC28061QDRQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC28061QDRQ1?
UCC28061QDRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC28061QDRQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC28061QDRQ1?
For technical support, including UCC28061QDRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC28061QDRQ1 requirements.
6.How does Aetrix verify that UCC28061QDRQ1 is sourced from the original manufacturer or authorized distributors?
All UCC28061QDRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28061QDRQ1 meets industry standards.
7.What is the process for return or replacement of UCC28061QDRQ1?
All UCC28061QDRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with UCC28061QDRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28061QDRQ1 part is unused and in its original packaging.
Return procedure for UCC28061QDRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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