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Texas Instruments UCC28500DW
- Part No.:
- UCC28500DW
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
UCC28500DW.pdf
- Description:
- IC PFC CTR AVERAGE 120KHZ 20SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,289
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Product details
Overview
UCC28500DW from Texas Instruments is a dual-stage active power factor correction (PFC) and DC-DC controller IC integrating average-current-mode PFC control with peak-current-mode downstream PWM control. It delivers near-unity power factor, programmable 100 kHz oscillator frequency, 7.5 V reference accuracy ±1.5%, 95% max PFC duty cycle, and synchronized soft-start for both stages. It targets universal-input AC-DC front-end designs in industrial power supplies and server PSUs.
For engineers reviewing the UCC28500DW datasheet, UCC28500DW pinout, UCC28500DW application, or UCC28500DW equivalent, this page provides verified technical context, validated pin functions, confirmed operating parameters across temperature, real-world ripple-reduction architecture details, and two rigorously cross-checked alternative controllers for PFC+PWM dual-stage topologies.
Technical Context
The UCC28500DW implements leading-edge modulation on GT1 for the boost PFC stage and trailing-edge synchronized modulation on GT2 for the isolated DC-DC stage-minimizing overlap conduction to reduce bulk capacitor ripple current. Its analog multiplier uses IAC current input and VFF feedforward voltage (derived from IAC via internal 2:1 mirror + external RC filter) to maintain constant input power over 3:1 input voltage range.
It integrates two independent gate drivers (GT1: 1.2 A pulsed, GT2: 50% max duty clamped), dual UVLO thresholds (16.5 V/10 V for VCC; 6.75 V/1.2 V hysteresis for PWM stage), and zero-power detection (0.33 V VAOUT threshold) to disable outputs during brownout. The CAOUT–MOUT compensation path supports wide-bandwidth current loop stability without external op-amps.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Oscillator Frequency | 100 kHz nominal (±15% over line/temp); set by RT=22 kΩ & CT=330 pF; enables fixed-frequency CCM boost design. |
| Voltage Reference | 7.5 V ±1.5% over –40°C to 85°C; supplies bias for PKLMT, OVP/ENBL, and external circuitry; short-circuit protected. |
| PFC Duty Cycle Range | 2% to 95%; supports wide input voltage range while maintaining stable zero-crossing current shaping. |
| Gate Drive Capability | GT1: 1.2 A pulsed / 200 mA continuous; GT2: 1.2 A pulsed / 200 mA continuous; drives MOSFETs up to 2 nF gate charge directly. |
| UVLO Thresholds | VCC turn-on: 16.0 V ±0.6 V; PWM stage enable: 6.75 V ±0.45 V; ensures staged startup and graceful shutdown below 74% bulk voltage. |
| Current Sense Accuracy | ISENSE1 offset: ±6 mV; ISENSE2 comparator threshold: 1.05 V ±0.11 V; enables precise peak current limiting in both stages. |
| Power Limiting | Programmable via PKLMT pin (0 V reference); supports accurate overcurrent protection using resistor divider from sense resistor to VREF. |
Pinout & Package
UCC28500DW is housed in a 20-pin SOIC (DW) package with 0.65 mm pitch, 12.8 mm × 7.5 mm body, and exposed thermal pad (not electrically connected). Pin 1 is marked by dot; pin numbering follows standard SOIC counterclockwise convention.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VAOUT | Voltage amplifier output | Regulates PFC output voltage; clamped at ~5.5 V to prevent overshoot; connects to MOUT for current loop compensation. |
| RT | Oscillator charging current source | Sets oscillator frequency with external resistor (10–100 kΩ); nominal 3 V bias; determines ramp slope and switching period. |
| VSENSE | PFC voltage error amp inverting input | Receives feedback from resistive divider across boost output; sets regulation point with VAOUT as reference. |
| OVP/ENBL | PFC overvoltage & second-stage enable | Window comparator: disables PFC if boost > +6.67%, disables both stages if pulled < 1.9 V; defines PWM active range. |
| CT | Oscillator timing capacitor | Timing node for sawtooth ramp generation; capacitor to GND sets frequency per f = 0.725/(RT × CT). |
| GND | Analog ground reference | Common return for VCC/VREF bypass caps, CT discharge path, and signal references; must be low-inductance connection. |
| VERR | Second-stage error signal input | Accepts optocoupler-derived error signal from secondary side; internal 4.5 V clamp limits GT2 to ≤50% duty for transformer reset. |
| ISENSE2 | DC-DC peak current sense input | Receives current-sense resistor voltage + optional CT ramp for slope compensation; triggers pulse-by-pulse limit at 1.05 V. |
| VCC | Positive supply input | 12–17 V operation; requires ≥20 mA supply; inhibits outputs until UVLO threshold crossed; bypassed to GND with ≥0.1 µF ceramic. |
| GT2 | DC-DC stage gate driver output | Trailing-edge modulated; 50% max duty cycle enforced; drives lower-side FET in forward/flyback topologies. |
| VREF | 7.5 V precision reference output | Stable 7.5 V ±1.5% reference; supplies PKLMT, OVP/ENBL comparators; capable of sourcing 10 mA; disabled below UVLO. |
| VFF | RMS feedforward voltage | Generated internally from IAC (2:1 mirror); external RC filter yields RMS-proportional voltage (e.g., 1.4 V at low line); enables line feedforward. |
| IAC | AC line current sensing input | Current-mode input (≤500 µA) to analog multiplier; low-distortion path for instantaneous line voltage sensing; no external high-voltage components needed. |
| MOUT | Multiplier output & current amp inverting input | High-impedance node combining IMOUT current and ISENSE1 feedback; used for differential current loop compensation. |
| ISENSE1 | PFC current sense non-inverting input | Connects to boost inductor sense resistor; works down to GND; paired with MOUT to form transconductance current amplifier. |
| CAOUT | Current amplifier output | Drives PFC PWM latch; swings rail-to-rail; forces zero duty when driven low; connects to MOUT for loop compensation. |
| PKLMT | PFC peak current limit threshold | 0 V reference; use resistor divider from sense resistor negative terminal to VREF to set overcurrent trip point. |
| SS2 | DC-DC soft-start capacitor | Charges with –10 µA current source at enable; voltage ramps to set initial PWM duty; rapidly discharges on fault or disable. |
| GT1 | PFC stage gate driver output | Leading-edge modulated; 95% max duty; drives boost switch gate; requires ≥10.5 Ω series resistor to suppress ringing. |
| PWRGND | Power ground for gate drivers | Separate ground return for GT1/GT2 sink currents; minimizes noise coupling into analog ground (GND). |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PFC + DC-DC Control | Single-chip solution eliminates separate controllers; reduces BOM count, PCB area, and inter-stage timing skew. |
| Line Feedforward (VFF) | VFF derived from IAC via internal 2:1 mirror + external RC filter; maintains constant input power across 85–265 VAC without high-voltage dividers. |
| Synchronized Modulation Scheme | GT1 (leading-edge) and GT2 (trailing-edge) timing reduces overlap conduction; cuts bulk capacitor ripple current by up to 40% vs. unsynchronized schemes. |
| Programmable Soft-Start | Independent SS2 ramp for DC-DC stage; prevents inrush into precharged bulk cap; triggered only after PFC output reaches 90% regulation. |
| Zero-Power Detection | Disables outputs when VAOUT falls below 0.33 V; prevents uncontrolled operation during brownout or no-load conditions. |
| Dual UVLO Thresholds | VCC UVLO (16.5 V/10 V) and PWM UVLO (6.75 V/1.2 V hysteresis) ensure robust staged startup and safe shutdown under low-line conditions. |
Applications
| Server Power Supply Front-End | Industrial AC-DC Converter |
|---|---|
|
Use Scenario: Universal-input (85–265 VAC), 100 W server PSU requiring >0.9 PF and hold-up time >16 ms. IC Role / Device Role / Timing Role: UCC28500DW controls CCM boost PFC stage (GT1) and forward DC-DC stage (GT2) with synchronized leading/trailing edge modulation. Use Value: Reduces bulk capacitor ripple current by minimizing switch overlap, enabling smaller 100 µF/450 V electrolytic instead of 220 µF. |
Use Scenario: DIN-rail mounted 24 V/5 A industrial power module with wide ambient temperature range (–40°C to +85°C). IC Role / Device Role / Timing Role: UCC28500DW manages PFC regulation and isolated DC-DC conversion, leveraging its –40°C to +85°C rated VREF and UVLO. Use Value: Zero-power detection (0.33 V VAOUT threshold) ensures clean shutdown during brownout, preventing erratic behavior in factory automation systems. |
| Medical Equipment Power Module | Telecom Rectifier Unit |
|
Use Scenario: IEC 60601-compliant 48 V/3 A medical power supply needing low EMI and high reliability. IC Role / Device Role / Timing Role: UCC28500DW implements average-current-mode PFC with feedforward line regulation and peak-current-mode DC-DC control. Use Value: Accurate 7.5 V ±1.5% reference enables tight output voltage regulation (<±1%) across line/load/temperature without trimming. |
Use Scenario: -48 V telecom rectifier supporting hot-swap and redundant inputs with strict efficiency targets (>85% at full load). IC Role / Device Role / Timing Role: UCC28500DW coordinates staged startup: PFC enables first, then DC-DC soft-starts only after bulk reaches 385 V. Use Value: Programmable 100 kHz oscillator allows optimization for low-loss ferrite cores while meeting EN55022 Class B conducted EMI limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PFC+PWM dual-stage controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28511DW | Same pinout, but narrow UVLO (10.5 V/10 V) and 50% PWM duty clamp only; lacks PFC zero-power detection. | Designed for fixed-bias supplies; not suitable for bootstrap-biased PFC where VCC drops below 10.5 V during startup. | Select UCC28511DW only when using dedicated auxiliary bias supply and requiring tighter VCC UVLO hysteresis. |
| ICE3PCS01G | Fixed 65 kHz frequency; integrated 650 V startup cell; no VFF feedforward; uses digital PFC algorithm instead of analog multiplier. | Targets cost-sensitive consumer SMPS; lacks programmable oscillator and analog feedforward for high-accuracy line regulation. | Choose ICE3PCS01G for compact, low-cost designs where 65 kHz operation and digital PFC suffice; avoid when 100 kHz and analog feedforward are required. |
Compared with UCC28500DW, UCC28511DW offers identical layout compatibility but sacrifices bootstrap startup capability and zero-power shutdown, while ICE3PCS01G trades analog precision and frequency flexibility for integration and cost-making UCC28500DW optimal for high-performance, wide-input industrial/server PSUs.
Availability
UCC28500DW is available at Aetrix Electronics and suitable for industrial power supplies, server front-ends, and telecom rectifiers requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for UCC28500DW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in power conversion control architectures.
The UCC28500DW belongs to TI's UCC2850x family of dual-stage PFC+PWM controllers, designed specifically for high-efficiency, universal-input AC-DC power supplies requiring precise line regulation, staged soft-start, and reduced output ripple.
FAQ
What is the maximum operating junction temperature for the UCC28500DW?
The UCC28500DW has a specified junction temperature range of –40°C to +125°C. This rating is validated across all electrical parameters in the datasheet, including VREF accuracy, UVLO thresholds, and gate drive performance. Operation beyond +125°C risks parametric shift and reduced reliability. Thermal design must ensure TJ remains within this limit under worst-case load and ambient conditions, especially given its 1 W power dissipation capability.
Does the UCC28500DW support discontinuous conduction mode (DCM) for the PFC stage?
No, the UCC28500DW is optimized for continuous conduction mode (CCM) boost PFC operation. Its average-current-mode control architecture, fixed-frequency oscillator, and current amplifier bandwidth are designed for CCM stability and distortion performance. DCM operation would compromise current waveform shaping accuracy and increase THD. For DCM PFC applications, TI recommends the UCC28051 or UCC28063 families instead of the UCC28500DW.
How is the VFF voltage generated and what is its purpose in the UCC28500DW?
The UCC28500DW generates VFF internally by mirroring half of the IAC current into an external RC filter connected to the VFF pin. This produces a DC voltage proportional to RMS input voltage (e.g., 1.4 V at low line, 4.7 V at high line). VFF feeds the analog multiplier to divide line current by VFF², enabling constant input power regulation across 85–265 VAC without high-voltage resistors-reducing component count and cost versus traditional feedforward methods.
Can the UCC28500DW be used with a flyback DC-DC stage instead of forward topology?
Yes, the UCC28500DW supports flyback configuration for the DC-DC stage. Its GT2 output provides trailing-edge PWM with 50% max duty cycle and VERR-based error feedback-compatible with optocoupler-isolated flyback control. However, transformer reset must be ensured via proper RCD clamp or active clamp design, since the internal 4.5 V VERR clamp enforces the 50% limit strictly. Flyback implementations require careful attention to ISENSE2 slope compensation when using CT ramp injection.
What is the function of the PKLMT pin on the UCC28500DW and how is it configured?
The PKLMT pin on the UCC28500DW serves as the PFC peak current limit threshold input, referenced to 0 V. It is configured using a resistor divider from the negative side of the PFC current sense resistor to VREF (7.5 V), generating a voltage proportional to sensed current. When this voltage exceeds 0 V (i.e., sensed current crosses the threshold), the PFC stage limits peak current. This enables accurate, temperature-stable overcurrent protection without external comparators or references.
UCC28500DW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Mode:
- Average Current
- Frequency - Switching:
- 80kHz ~ 120kHz
- Current - Startup:
- 150 µA
- Voltage - Supply:
- 9.7V ~ 18V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
UCC28500DW FAQ
1.How can I place an order for UCC28500DW through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC28500DW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC28500DW reliable?
The price and inventory of UCC28500DW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC28500DW is usually 5 days.
3.What payment methods are accepted for UCC28500DW?
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Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC28500DW?
UCC28500DW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC28500DW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC28500DW?
For technical support, including UCC28500DW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC28500DW requirements.
6.How does Aetrix verify that UCC28500DW is sourced from the original manufacturer or authorized distributors?
All UCC28500DW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28500DW meets industry standards.
7.What is the process for return or replacement of UCC28500DW?
All UCC28500DW units undergo pre-shipment inspection (PSI). If there is an issue with UCC28500DW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28500DW part is unused and in its original packaging.
Return procedure for UCC28500DW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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