Texas Instruments UCC28502DWG4
- Part No.:
- UCC28502DWG4
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
UCC28502DWG4.pdf
- Description:
- IC PFC CTR AVERAGE 100KHZ 20SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UCC28502DWG4 from Texas Instruments is a dual-stage active power factor correction (PFC) and DC-DC controller IC integrating average-current-mode PFC with peak-current-mode downstream PWM control. It delivers near-unity power factor, programmable 80–120 kHz oscillator frequency, 16.5 V/10 V wide UVLO threshold for bootstrap bias operation, and synchronized leading-edge (PFC) / trailing-edge (PWM) modulation to minimize bulk capacitor ripple. It targets universal-input AC-DC front-end designs in industrial power supplies.
For engineers reviewing the UCC28502DWG4 datasheet, UCC28502DWG4 pinout, UCC28502DWG4 application, or UCC28502DWG4 equivalent, key selection criteria include its dual-stage control architecture, PFC overvoltage protection at VREF + 0.5 V, second-stage soft-start via SS2 pin, and compatibility with continuous-conduction-mode boost PFC followed by forward or flyback DC-DC topologies.
Technical Context
The UCC28502DWG4 implements a two-stage control architecture: the PFC section uses average current-mode control with line-voltage feedforward (VFF) derived from IAC mirroring and a single-pole external filter, enabling stable input power regulation across 85–265 VRMS inputs. Its multiplier divides line current by VFF² to achieve accurate power limiting and low THD.
The second stage employs peak current-mode control with externally generated error signal fed into VERR, internal 50% duty-cycle clamp, and programmable UVLO2 (6.75 V turn-on, 3.0 V hysteresis) allowing operation down to 50% of nominal bulk voltage. Synchronization between GT1 (PFC gate drive) and GT2 (PWM gate drive) ensures minimal switch overlap and reduced output capacitor stress.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Oscillator Frequency | 80–120 kHz; set by RT/CT network; initial accuracy ±15 kHz at 25°C enables stable timing without external crystal. |
| PFC UVLO Threshold | 16.5 V turn-on / 10 V turn-off; wide hysteresis (6.3 V) supports reliable bootstrap startup under varying input conditions. |
| Second-Stage UVLO2 | 6.75 V turn-on with 3.0 V hysteresis; allows PWM operation down to 50% of bulk voltage, critical for brownout resilience. |
| Voltage Reference | 7.5 V ±15 mV over –40°C to 85°C; powers external circuitry and serves as precision reference for PKLMT and OVP thresholds. |
| Gate Drive Capability | GT1/GT2: 1.2 A pulsed, 200 mA continuous; low pull-up/pull-down resistance (5–12 Ω) enables direct MOSFET driving without buffer stages. |
| Zero-Power Detection | 0.33 V threshold on VAOUT; disables PFC output when boost output falls below safe operating level, preventing unregulated discharge. |
| Multiplier Gain Constant | 0.5–1.5 V⁻¹; linearly scales IAC-based current command with VAOUT, enabling precise power shaping across load range. |
Pinout & Package
UCC28502DWG4 is housed in a 20-pin SOIC (DW) package with exposed thermal pad, rated for –40°C to 85°C operation. Pin assignments are fully defined per TI SLUS419C Rev. November 2001.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GT1 | PFC gate driver output | Drives high-side boost MOSFET; supports 93–100% duty cycle; requires ≥10.5 Ω series gate resistor to suppress overshoot. |
| GT2 | DC-DC gate driver output | Drives PWM stage FET; internally clamped to ≤50% duty cycle to ensure transformer reset in forward topologies. |
| IAC | AC line current sensing input | Current-mode input (≤500 µA) feeding analog multiplier; enables distortion-free RMS feedforward via VFF mirroring. |
| VFF | RMS feedforward voltage node | Generated by mirroring IAC through external RC filter; sets VFF = 1.4 V at low line, scaling with VAC² for constant-power regulation. |
| SS2 | Second-stage soft-start control | Charges external capacitor during enable; voltage ramps to set PWM duty cycle gradually, preventing inrush into downstream converter. |
| OVP/ENBL | PFC overvoltage & enable input | Window comparator: disables PFC if VAOUT > VREF+0.5 V; disables both stages if pulled <1.9 V, enabling system-level shutdown. |
| PKLMT | PFC peak current limit threshold | 0 V reference; external resistor divider from current-sense resistor negative terminal to VREF sets overcurrent trip point. |
| VERR | Second-stage error amplifier input | Accepts opto-coupled secondary-side error signal; internal 4.5 V clamp enforces ≤50% duty cycle for safe transformer reset. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual-stage control | Single IC replaces discrete PFC + PWM controllers; eliminates inter-stage timing mismatches and reduces BOM count by ≥30%. |
| Leading-edge/trailing-edge synchronization | GT1 (leading) and GT2 (trailing) timing minimizes conduction overlap, reducing bulk capacitor RMS ripple current by up to 40% vs unsynchronized designs. |
| Programmable soft-start for second stage | SS2 pin controls ramp rate of PWM duty cycle; prevents output overvoltage and transformer saturation during cold start. |
| Accurate power limiting | Multiplier-based IMOUT × VFF product maintains constant input power across line variations; eliminates need for external power metering circuits. |
| Wide-range UVLO2 for brownout tolerance | 6.75 V turn-on with 3.0 V hysteresis allows second-stage operation down to 50% of nominal bulk voltage, supporting holdup during deep sags. |
Applications
| Industrial AC-DC Power Supplies | Medical Equipment Power Front Ends |
|---|---|
Use Scenario: 85–265 VRMS universal-input power supply delivering 12 V/10 A for PLC controllers with 16 ms holdup requirement. IC Role / Device Role / Timing Role: UCC28502DWG4 performs average-current-mode PFC control and synchronized peak-current-mode forward converter regulation. Use Value: Achieves >0.99 power factor and <5% THD while enabling single-chip coordination of PFC and DC-DC startup sequencing. | Use Scenario: Isolated 24 V/5 A power module for diagnostic imaging equipment requiring low EMI and strict safety compliance. IC Role / Device Role / Timing Role: UCC28502DWG4 manages boost PFC stage and opto-coupled feedback-controlled forward converter with transformer reset assurance. Use Value: Internal 50% duty-cycle clamp on GT2 and VERR clamping guarantee safe transformer demagnetization, meeting IEC 60601 creepage requirements. |
| Server PSU Front-End Modules | LED Driver Power Stages |
Use Scenario: 385 V DC bus generator for 1U server PSUs operating from 100–240 V AC with active cooling constraints. IC Role / Device Role / Timing Role: UCC28502DWG4 controls CCM boost PFC and regulates downstream half-bridge DC-DC with precise VFF feedforward. Use Value: VFF-based line feedforward maintains constant input power across full input range, eliminating output voltage droop during brownouts. | Use Scenario: High-efficiency 48 V/3 A constant-current LED driver for outdoor signage with universal AC input and thermal derating. IC Role / Device Role / Timing Role: UCC28502DWG4 executes PFC and drives isolated flyback converter with zero-power detection for graceful shutdown. Use Value: Zero-power comparator (0.33 V threshold on VAOUT) disables PFC when output falls below safe level, preventing uncontrolled LED dimming or flicker. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-stage PFC + DC-DC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28502DWR | Same die, tape-and-reel packaging (2000/reel); identical electrical specs and pinout. | No functional difference; selected for automated SMT assembly vs. tube-packaged DWG4. | Choose UCC28502DWR for volume production; UCC28502DWG4 for prototyping or low-volume builds. |
| UCC28070 | Dual-phase interleaved PFC only; no integrated DC-DC controller; requires separate PWM IC. | Used where higher PFC power (>300 W) or lower EMI is required; lacks second-stage gate drivers and UVLO2 logic. | Select UCC28070 only when PFC performance outweighs integration benefits; UCC28502DWG4 remains optimal for compact 100–250 W systems. |
Compared with UCC28502DWR, the UCC28502DWG4 offers identical functionality in tube packaging for flexibility in small-batch builds; versus UCC28070, it provides full two-stage integration-eliminating inter-IC timing skew, reducing PCB area by 35%, and simplifying startup sequencing-but trades off interleaved PFC capability.
Availability
UCC28502DWG4 is available at Aetrix Electronics and suitable for industrial AC-DC power supplies, medical equipment front ends, and server PSU modules requiring stable component supply and long-term design continuity.
Supply support for UCC28502DWG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 50 years of power conversion innovation.
The UCC2850x product line was engineered specifically for cost-sensitive, high-efficiency AC-DC power supplies requiring integrated PFC and isolated DC-DC control in a single package.
FAQ
What is the recommended gate resistor value for GT1 when using UCC28502DWG4 with a 15-V VCC supply?
Per TI SLUS419C Figure 4, the minimum recommended gate resistor for GT1 is 10.5 Ω at 15 V VCC to prevent excessive overshoot when driving capacitive MOSFET gates. This value balances rise/fall time control (25–50 ns typical) against driver stress. Lower values risk ringing; higher values increase switching losses. Always verify with actual MOSFET gate charge and layout parasitics in final UCC28502DWG4 design.
How does the UCC28502DWG4 implement line feedforward, and what external components are required?
The UCC28502DWG4 generates VFF by mirroring IAC current (≤500 µA) to the VFF pin, then applying an external single-pole RC filter (e.g., 100 kΩ + 10 nF) to attenuate 120-Hz ripple. At low line, VFF = 1.4 V; it scales with VAC² to maintain constant input power. No high-voltage components are needed-this topology replaces traditional resistive divider feedforward networks and reduces part count by ≥4 components in UCC28502DWG4 designs.
Can UCC28502DWG4 support discontinuous conduction mode (DCM) PFC operation?
No-UCC28502DWG4 is optimized for continuous conduction mode (CCM) boost PFC operation only. Its average-current-mode control loop, fixed-frequency oscillator, and VFF feedforward architecture assume CCM operation across the full input range (85–265 VRMS). DCM operation would cause instability in the multiplier-based current command and inaccurate power limiting; TI explicitly specifies CCM use in SLUS419C Section "Typical Application".
What is the function of the PKLMT pin on UCC28502DWG4, and how is the PFC overcurrent threshold set?
The PKLMT pin on UCC28502DWG4 provides a 0 V reference for PFC peak current limiting. To set the overcurrent threshold, connect a resistor divider from the negative side of the PFC current-sense resistor to VREF (7.5 V), scaling the sensed voltage so that the divider output equals 0 V at the desired current limit. For example, a 10 mΩ sense resistor with 10 A peak current requires 100 mV across it; a 1:75 divider (1 kΩ to PKLMT, 74 kΩ to VREF) achieves this. The UCC28502DWG4 triggers shutdown when PKLMT exceeds 0 V.
Does UCC28502DWG4 provide built-in protection against output overvoltage in the PFC stage?
Yes-UCC28502DWG4 includes dedicated PFC overvoltage protection via the OVP/ENBL pin. When VAOUT exceeds VREF + 0.500 V (i.e., ~8.0 V), the internal window comparator disables GT1, halting PFC switching. Hysteresis of 300–600 mV prevents chatter. This protection is independent of the second-stage UVLO2 and operates even if the DC-DC section is disabled, ensuring robust 385 V bulk bus regulation in UCC28502DWG4 applications.
UCC28502DWG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Mode:
- Average Current
- Frequency - Switching:
- 100kHz
- Current - Startup:
- 150 µA
- Voltage - Supply:
- 9.7V ~ 18V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
UCC28502DWG4 FAQ
1.How can I place an order for UCC28502DWG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC28502DWG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC28502DWG4 reliable?
The price and inventory of UCC28502DWG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC28502DWG4 is usually 5 days.
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UCC28502DWG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC28502DWG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC28502DWG4?
For technical support, including UCC28502DWG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC28502DWG4 requirements.
6.How does Aetrix verify that UCC28502DWG4 is sourced from the original manufacturer or authorized distributors?
All UCC28502DWG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28502DWG4 meets industry standards.
7.What is the process for return or replacement of UCC28502DWG4?
All UCC28502DWG4 units undergo pre-shipment inspection (PSI). If there is an issue with UCC28502DWG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28502DWG4 part is unused and in its original packaging.
Return procedure for UCC28502DWG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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