Texas Instruments UCC28503DW

Overview

UCC28503DW from Texas Instruments is a dual-stage active power factor correction (PFC) and DC-DC controller IC for off-line AC-DC power supplies. It integrates average-current-mode PFC with trailing-edge synchronized peak-current-mode second-stage control, supports 85–265 V_RMS universal input, delivers near-unity power factor (>0.99), and features programmable 80–120 kHz oscillator frequency, 10.5 V/10 V narrow UVLO for fixed-bias operation, and 50% max duty cycle clamp on GT2.

For engineers reviewing the UCC28503DW datasheet, UCC28503DW pinout, UCC28503DW application, or UCC28503DW equivalent, this page provides verified technical context, validated pin functions, confirmed operating parameters, real-world application mappings, and two rigorously cross-checked alternative controllers for PFC + isolated DC-DC systems.

Technical Context

The UCC28503DW implements a two-stage control architecture: the PFC stage uses average current-mode control with line-voltage feedforward (VFF) derived from IAC mirroring and a single-pole external filter, enabling stable power regulation across 3:1 input voltage range; its leading-edge modulation minimizes overlap with the second stage. The downstream DC-DC section employs peak current-mode control with externally generated error signal fed via VERR, internal soft-start (SS2), and programmable UVLO2 threshold (6.75 V turn-on, 3.0 V hysteresis) for operation down to 50% of nominal bulk voltage.

Key analog blocks include a 7.5 V precision reference (±15 mV over –40°C to 85°C), low-offset current amplifier (±6 mV input offset), high-linearity multiplier (K = 0.5–1.5 V⁻¹), and dual totem-pole gate drivers (GT1/GT2) with 5–12 Ω pull-up/pull-down resistance and sub-50 ns rise/fall times into 1 nF load.

Key Specifications

Pinout & Package

UCC28503DW is housed in a 20-pin SOIC (DW) package with 0.300-inch body width and standard JEDEC MS-013 footprint. Pin assignments are identical to the N-package variant per TI SLUS419C Rev. November 2001.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-stage PFC + DC-DC controller applications.

Compared with UCC28502DW and UCC38503DW, the UCC28503DW uniquely balances narrow fixed-bias PFC UVLO with extended industrial temperature rating, making it the sole option for ruggedized 2-stage supplies requiring reliable startup at cold temperatures without auxiliary winding complexity.

Availability

UCC28503DW is available at Aetrix Electronics and suitable for server power supplies, industrial motor drive PSUs, medical imaging equipment PSUs, and telecom rectifier modules requiring stable component supply across long production lifecycles.

Supply support for UCC28503DW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and power management solutions for industrial, automotive, and communications markets.

The UCC2850x product line was designed specifically for integrated active PFC and isolated DC-DC control in universal-input AC-DC power supplies, targeting efficiency, reliability, and reduced system component count.

FAQ

What is the purpose of the VFF pin on the UCC28503DW?

The VFF pin on the UCC28503DW provides RMS line-voltage feedforward by mirroring the IAC current through an external RC filter. This generates a voltage proportional to input line RMS value (1.4 V at low line, 4.7 V at high line), enabling constant input power regulation across 85–265 V_RMS input range without high-voltage sensing components. Its use is mandatory for stable PFC operation per TI SLUS419C.

How does the UCC28503DW handle start-up sequencing between the PFC and DC-DC stages?

The UCC28503DW internally sequences start-up by holding the second stage disabled until the PFC output reaches within 10% of regulation, then initiating SS2 soft-start. If the PFC output drops below 50% of nominal (UVLO2 threshold), the DC-DC stage shuts down. This prevents overstress during brownouts and eliminates need for external sequencing logic - a core function confirmed in the device block diagram and typical application circuits.

What is the maximum allowable duty cycle on GT2 of the UCC28503DW?

The UCC28503DW hardware-clamps the GT2 output to a maximum duty cycle of 50%, as specified in the Electrical Characteristics table (page 5) and enforced by internal logic to guarantee transformer reset in forward and flyback topologies. This limit is independent of external component values and cannot be overridden - a key safety feature for isolated DC-DC stage reliability.

Can the UCC28503DW operate with a 5-V bias supply?

No, the UCC28503DW requires a minimum VCC of 12 V for normal operation, with absolute maximum rating of 18 V. Its narrow UVLO threshold (10.5 V turn-on) means operation below 12 V risks intermittent enable/disable cycling. A 5-V rail cannot power UCC28503DW directly; a dedicated bias supply or auxiliary winding generating ≥12 V is mandatory per Absolute Maximum Ratings and Functional Description sections.

What is the function of the PKLMT pin on the UCC28503DW?

The PKLMT pin on the UCC28503DW serves as the PFC peak current limit threshold input, referenced to 0 V. A resistor divider from the negative side of the current-sense resistor to VREF sets the overcurrent trip point - for example, a 100 mΩ sense resistor with 1 V drop requires a 10 kΩ:75 kΩ divider (to 7.5 V) to trigger at 10 A. This function is explicitly defined in the Pin Assignments section (page 6) and confirmed in the Typical Application schematic (Figure 9).