Texas Instruments UCC28503DWTR

Overview

UCC28503DWTR from Texas Instruments is a dual-stage active power factor correction (PFC) and DC-DC controller IC integrating average-current-mode PFC with peak-current-mode downstream PWM control. It delivers near-unity power factor, programmable 80–120 kHz oscillator frequency, 10.5 V/10 V narrow UVLO for fixed-bias operation, and synchronized leading-edge (PFC) / trailing-edge (PWM) modulation to minimize bulk-capacitor ripple. Used in universal-input AC-DC supplies such as server PSUs and industrial power adapters.

For engineers reviewing the UCC28503DWTR datasheet, UCC28503DWTR pinout, UCC28503DWTR application, or UCC28503DWTR equivalent, key selection criteria include its dual-stage control architecture, PFC+PWM synchronization capability, 50% max duty cycle clamp on GT2, -40°C to 85°C operating range, and DW package compatibility with tape-and-reel procurement.

Technical Context

The UCC28503DWTR implements average-current-mode control in the PFC stage using IAC current sensing and VFF feedforward derived from mirrored IAC through an external RC filter, enabling stable input power regulation across 85–265 V_RMS inputs. Its multiplier output (MOUT) scales line current by VAOUT/(VFF)², supporting accurate power limiting and low-distortion shaping.

The second-stage PWM section uses external error feedback via VERR, features programmable soft-start (SS2), 6.75 V turn-on threshold with 3.0 V hysteresis for UVLO2, and pulse-by-pulse current limiting referenced to ISENSE2. GT2 is internally clamped to ≤50% duty cycle to ensure transformer reset in forward/isolated topologies.

Key Specifications

Pinout & Package

UCC28503DWTR is housed in a 20-pin SOIC (DW) package with exposed thermal pad, rated for –40°C to 85°C operation and compatible with standard surface-mount reflow profiles.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-stage PFC+PWM controller applications.

Compared with UCC28501DWTR, UCC28503DWTR provides wider second-stage UVLO2 hysteresis (3.0 V vs 0.5 V) for robust operation during PFC output sag, while UCC28070DR lacks integrated PWM control entirely-requiring external coordination and increasing board area and BOM cost.

Availability

UCC28503DWTR is available at Aetrix Electronics and suitable for server power supplies, industrial AC-DC adapters, and medical equipment power modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for UCC28503DWTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions, with decades of expertise in power management IC design and manufacturing.

The UCC2850x product line was engineered specifically for cost-sensitive, high-efficiency AC-DC power conversion systems requiring integrated PFC and isolated DC-DC control in a single package.

FAQ

What is the UVLO behavior of the UCC28503DWTR and how does it differ from other UCC2850x variants?

The UCC28503DWTR features a narrow 10.5 V turn-on / 10 V turn-off UVLO on VCC, optimized for fixed auxiliary bias supplies. Its second-stage UVLO2 has a 6.75 V turn-on threshold with 3.0 V hysteresis-enabling DC-DC operation down to 50% of nominal bulk voltage. This differs from UCC28501DWTR (same VCC UVLO but only 0.5 V UVLO2 hysteresis) and UCC28500DWTR (16.5 V/10 V VCC UVLO for bootstrap use). The UCC28503DWTR's UVLO2 profile ensures robust restart after deep PFC output sags.

How does the UCC28503DWTR implement line voltage feedforward without high-voltage components?

The UCC28503DWTR generates VFF by mirroring the IAC current input (≤500 µA) through an internal 2:1 current mirror to the VFF pin, where an external RC filter produces a voltage proportional to RMS line voltage. This eliminates the need for high-voltage resistive dividers or transformers, reducing cost and improving safety. The VFF signal then scales the multiplier output as 1/(VFF)², maintaining constant input power across 85–265 V_RMS inputs without high-side sensing components.

What is the function of the PKLMT pin on the UCC28503DWTR and how is it configured?

The PKLMT pin on the UCC28503DWTR serves as the PFC peak current limit threshold reference, fixed at 0 V. To set the overcurrent trip point, a resistor divider connects the negative side of the PFC current-sense resistor to VREF (7.5 V), level-shifting the sensed voltage so that the voltage across the sense resistor equals the desired current threshold × R_sense. For example, with R_sense = 0.1 Ω and desired limit = 10 A, the divider must produce 1.0 V at PKLMT-achievable with a 10 kΩ resistor from PKLMT to GND and 65 kΩ from VREF to PKLMT. This configuration enables precise, temperature-stable current limiting.

Can the UCC28503DWTR be used in discontinuous conduction mode (DCM) PFC applications?

No, the UCC28503DWTR is specifically designed for continuous conduction mode (CCM) boost PFC operation. Its average-current-mode control architecture, internal multiplier transfer function, and VFF feedforward implementation assume CCM operation with predictable inductor current waveform. DCM operation would distort the IAC-to-MOUT relationship and degrade power factor correction accuracy. For DCM PFC applications, TI recommends alternatives such as the UCC28051 or UCC28061, which are optimized for boundary/DCM control.

How does the UCC28503DWTR coordinate startup sequencing between the PFC and DC-DC stages?

The UCC28503DWTR coordinates startup by monitoring VAOUT-the output of the PFC voltage amplifier. It holds the DC-DC stage disabled until VAOUT reaches ≥90% of the target boost output voltage. Once enabled, SS2 initiates a controlled soft-start ramp on the DC-DC stage, preventing inrush current overload on the PFC bulk capacitor. If VAOUT later drops below the UVLO2 threshold (e.g., due to overload or AC loss), the DC-DC stage shuts down immediately while the PFC continues regulating-ensuring graceful degradation and system protection. This sequencing is fully internal and requires no external logic.