My Inquiry
My Account
Texas Instruments UCC28513DWR
- Part No.:
- UCC28513DWR
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
UCC28513DWR.pdf
- Description:
- IC PFC CTR AVERAGE 200KHZ 20SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,900
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UCC28513DWR from Texas Instruments is a dual-stage PFC/PWM controller IC for off-line AC-DC power supplies compliant with IEC 61000-3-2 harmonic standards. It integrates average-current-mode PFC and peak-current-mode PWM control, supports 1:1 PFC:PWM frequency ratio, features 2-A source/3-A sink gate drivers (GT1/GT2), 200-kHz typical switching frequency, and operates from –40°C to +105°C. Used in industrial and telecom AC-DC front-ends requiring high power factor and regulated DC output.
For engineers reviewing the UCC28513DWR datasheet, UCC28513DWR pinout, UCC28513DWR application, or UCC28513DWR equivalent, key selection criteria include UVLO turn-on at 10.2 V, PWM UVLO2 turn-off at 3.55 V, programmable maximum duty cycle via D_MAX pin, and compatibility with boost PFC + flyback/buck-derived PWM topologies.
Technical Context
The UCC28513DWR implements leading-edge modulation for the PFC stage and trailing-edge modulation for the PWM stage to minimize ripple current in the boost output capacitor. Its PFC section uses average-current-mode control with input voltage feedforward (VFF), a highly linear three-input multiplier, and a transconductance voltage amplifier (VAOUT) with slew-rate enhancement.
The PWM stage employs peak-current-mode control with slope compensation via CT_BUFF, programmable soft-start (SS2), accurate maximum duty cycle clamping (D_MAX), and independent UVLO2 (3.55 V turn-off). Startup sequencing ensures PWM activation only after PFC output reaches 90% of regulation, and PWM remains active until PFC output drops to 47% of nominal.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PFC:PWM Frequency Ratio | 1:1 - PFC and PWM stages switch at identical frequency (e.g., 200 kHz), simplifying EMI filter design and enabling synchronized ripple cancellation. |
| VCC UVLO Turn-On / Turn-Off | 10.2 V / 9.7 V - Ensures reliable startup under brownout conditions while preventing oscillation near threshold. |
| PWM UVLO2 Turn-Off Threshold | 3.55 V - Delays PWM shutdown until PFC bus has significantly collapsed (47% of nominal), improving hold-up time robustness. |
| Gate Drive Capability (GT1/GT2) | 2-A source / 3-A sink - Directly drives medium-power MOSFETs without external buffers in 300–500 W designs. |
| Reference Voltage (VREF) | 7.5 V ±15 mV - Precision internal reference powers external circuitry (e.g., optocoupler bias, divider networks) with <5 mV load regulation up to 6 mA. |
| Maximum Duty Cycle Clamp | 75% typical at D_MAX = 4.15 V - Prevents transformer saturation in flyback or forward converters by limiting on-time during overload or startup. |
| Zero Power Detect Threshold | 0.33 V (falling edge) - Disables GT1 when VAOUT falls below threshold, eliminating standby losses in no-load or AC dropout conditions. |
Pinout & Package
UCC28513DWR is housed in a 20-pin SOIC (DW) package with 1.27-mm pitch, thermally enhanced for surface-mount assembly in high-density power supplies.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GT1 (12) | PFC gate driver output | 2-A source / 3-A sink totem-pole output driving boost MOSFET; disabled outside UVLO window. |
| GT2 (10) | PWM gate driver output | Identical drive strength to GT1; controlled by PWM comparator and D_MAX clamp. |
| VSENSE (3) | PFC voltage error amplifier inverting input | Feedback node for PFC output voltage regulation; also feeds OVP, ENABLE, and UVLO2 comparators. |
| VAOUT (1) | PFC transconductance amplifier output | Regulates PFC bus voltage; sources/sinks up to 30 µA linearly, 3.3 mA during slew enhancement; enables zero-power detect. |
| IAC (18) | PFC multiplier current input | Accepts rectified line voltage-derived current (≤500 µA); sets PFC reference magnitude proportional to VAC2. |
| VFF (19) | PFC voltage feedforward input | Sources IAC/2 current; external RC filter generates feedforward signal to maintain constant power across line range. |
| ISENSE1 (16) | PFC current amplifier non-inverting input | Connects to ground side of PFC sense resistor; forms current loop with MOUT and CAOUT for stable CCM operation. |
| ISENSE2 (8) | PWM current sense input | Receives voltage from PWM sense resistor; 1.3-V peak threshold with 1.5-V internal level shift for noise immunity. |
| VERR (7) | PWM error amplifier input | Feedback from secondary-side optocoupler; controls GT2 duty cycle; clamped to 3 V max for full-on capability. |
| D_MAX (4) | PWM maximum duty cycle control | Analog input (0.09–0.90 V) linearly sets GT2 duty limit; 4.15 V yields ~75% typical max duty. |
| SS2 (13) | PWM soft-start timing | Capacitor-to-ground sets PWM ramp duration; internal 10.5-µA current charges SS2 to 3 V for controlled startup. |
| PKLMT (14) | PFC peak current limit | Voltage input referenced to 0 V; sets overcurrent threshold across PFC sense resistor using resistor divider from VREF. |
| CAOUT (15) | PFC current amplifier output | Drives PFC PWM comparator; connects to MOUT for loop compensation; swings rail-to-rail for full duty control. |
| MOUT (17) | PFC multiplier output / current amp input | Current-output node tied to ISENSE1; sets PFC power range and gain via external resistor to sense resistor. |
| CT_BUFF (5) | PWM oscillator ramp buffer | 4-V peak-to-peak buffered ramp; used with resistor to ISENSE2 for slope compensation in peak-current-mode control. |
| RT (2) | Oscillator frequency programming | Resistor-to-GND sets CT_BUFF frequency (65–600 kHz); determines both PFC and PWM switching frequency. |
| VREF (20) | 7.5-V precision reference output | Stable 7.5-V supply for external circuits; delivers >10 mA with <5-mV load regulation; short-circuit protected. |
| GND (6) | Analog ground reference | Signal ground for all analog blocks; must be Kelvin-connected to PWRGND (11) for low-noise operation. |
| PWRGND (11) | Power ground return | High-current return path for GT1/GT2 drivers; externally tied to GND with minimal impedance. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PFC + PWM control | Eliminates inter-stage timing mismatches and reduces BOM count by merging two controllers into one 20-pin SOIC device. |
| Leading-edge PFC + trailing-edge PWM modulation | Reduces boost capacitor RMS current by >30% versus dual trailing-edge schemes, lowering thermal stress and size. |
| Programmable PWM maximum duty cycle | Enables safe operation in two-transistor forward or flyback topologies where duty cycle must be limited to avoid core saturation. |
| Independent PWM UVLO2 with 3.55-V turn-off | Extends hold-up time by keeping PWM active longer during AC dropout-critical for medical and industrial systems meeting IEC 60601 or EN 50178. |
| Zero power detect with 0.33-V threshold | Forces GT1 shutdown when VAOUT falls below 0.33 V, cutting PFC stage quiescent consumption to <150 µA in no-load condition. |
| 2-A/3-A gate drivers with 16-ns rise / 7-ns fall | Drives 10-nF MOSFET gates directly at 200 kHz without external buffers, reducing layout complexity and gate drive losses. |
Applications
| Industrial AC-DC Power Supplies | Telecom Rectifier Modules |
|---|---|
Use Scenario: 300–500 W offline power supply for PLCs, motor drives, and factory automation equipment operating from universal AC input (85–265 VAC). IC Role / Device Role / Timing Role: UCC28513DWR serves as the primary controller for boost PFC followed by isolated flyback or half-bridge PWM, managing both stages' modulation, sequencing, and protection. Use Value: Meets IEC 61000-3-2 Class A harmonic limits, achieves >0.99 PF at full load, and sustains regulated output during 20-ms AC dropout via 47% PFC bus hold-down logic. | Use Scenario: -48 V telecom rectifier module with hot-swap capability and redundant AC inputs feeding distributed DC power buses. IC Role / Device Role / Timing Role: UCC28513DWR regulates PFC bus to 380–400 VDC and controls downstream LLC or phase-shifted full-bridge PWM, coordinating startup and fault recovery. Use Value: Programmable D_MAX prevents transformer saturation during inrush; UVLO2 hysteresis (3.55 V turn-off) extends hold-up beyond 15 ms per GR-1089-CORE, supporting battery backup switchover. |
| Medical Equipment Power Front-Ends | Server PSU Auxiliary Power Rails |
Use Scenario: Primary AC-DC conversion stage in diagnostic imaging systems (e.g., ultrasound, MRI support electronics) requiring low EMI and high reliability. IC Role / Device Role / Timing Role: UCC28513DWR implements LEM/TEM modulation to suppress conducted EMI in the 150 kHz–30 MHz band and provides OVP/UVLO2/zero-power detection for safety compliance. Use Value: Reduced boost capacitor ripple lowers thermal derating needs; zero-power detect cuts no-load input power to <300 mW, aiding ENERGY STAR Tier 2 compliance. | Use Scenario: Standby and auxiliary power generation in 1U/2U server PSUs, powering BMC, fans, and sequencing logic before main rail activation. IC Role / Device Role / Timing Role: UCC28513DWR manages a dedicated low-power boost PFC + flyback stage delivering +5 VSB and +12 V AUX, with independent soft-start and sequencing. Use Value: SS2-programmable soft-start prevents inrush into bulk capacitors; VREF powers optocoupler and supervisor ICs with <5 mV drift, ensuring precise auxiliary rail regulation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PFC/PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28512DWR | Higher UVLO turn-on (16 V) and PWM UVLO2 turn-off (3.55 V); same 1:1 frequency ratio and pinout. | Better suited for high-line-only or wide-input-range designs where early startup is not required and higher hold-up margin is critical. | Select UCC28512DWR if system requires 16-V UVLO for improved noise immunity on VCC rail, or if 3.55-V UVLO2 hold-down matches existing PFC bus design. |
| UCC28070DWR | Dedicated average-current-mode PFC controller only (no integrated PWM); 8-pin SOIC; requires external PWM IC. | Used in modular designs where PFC and PWM stages are separated for serviceability or thermal management. | Choose UCC28070DWR when design flexibility, lower gate drive current (1-A), or independent optimization of PFC/PWM timing is prioritized over integration. |
Compared with UCC28512DWR, the UCC28513DWR offers earlier startup (10.2 V vs. 16 V) for brownout resilience but retains identical 3.55-V PWM hold-down and 1:1 frequency ratio; versus UCC28070DWR, it trades modularity for reduced component count and guaranteed synchronization between PFC and PWM stages.
Availability
UCC28513DWR is available at Aetrix Electronics and suitable for industrial AC-DC power supplies, telecom rectifier modules, and medical equipment front-ends requiring stable component supply, long-term lifecycle support, and IEC 61000-3-2 compliance.
Supply support for UCC28513DWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in power conversion ICs.
The UCC28513DWR belongs to TI's UCC2851x family of combination PFC/PWM controllers, designed specifically for cost-sensitive, high-efficiency offline power supplies needing IEC 61000-3-2 compliance and simplified system-level design.
FAQ
What is the UVLO turn-on and turn-off threshold for UCC28513DWR?
The UCC28513DWR has a VCC undervoltage lockout (UVLO) turn-on threshold of 10.2 V and a turn-off threshold of 9.7 V. This 0.5-V hysteresis prevents oscillation during marginal input conditions. The PWM-specific UVLO2 turns off at 3.55 V, allowing continued operation until the PFC bus drops to 47% of nominal-critical for maintaining hold-up time in AC dropout scenarios. These thresholds are factory-trimmed and specified over temperature.
How does UCC28513DWR implement zero power detection?
The UCC28513DWR monitors the VAOUT pin voltage to detect zero power conditions. When VAOUT falls below 0.33 V (falling edge), the internal zero power comparator disables GT1, halting PFC switching and reducing quiescent supply current to <150 µA. This feature is enabled automatically and requires no external components-it leverages the same VAOUT node used for PFC voltage regulation, ensuring tight coupling between output collapse and shutdown.
Can UCC28513DWR drive MOSFETs directly without external gate drivers?
Yes, UCC28513DWR can drive MOSFETs directly: its GT1 and GT2 outputs each deliver 2-A peak source and 3-A peak sink current with 16-ns rise and 7-ns fall times into 1-nF loads. This supports direct drive of MOSFETs with gate charges up to ~20 nC at 200 kHz. For higher gate charge devices or layouts with long traces, a small series resistor (~2 Ω) is recommended to dampen ringing, as noted in the datasheet's GT1/GT2 descriptions.
What is the function of the CT_BUFF pin on UCC28513DWR?
The CT_BUFF pin on UCC28513DWR provides a buffered 4-V peak-to-peak version of the internal PWM oscillator ramp signal. It is designed to connect directly to ISENSE2 via a single resistor for slope compensation in peak-current-mode control-eliminating need for external op-amps or timing components. The internal buffer drives typical 500-µA resistive loads, ensuring stable ramp injection even with PCB parasitics, and is active only when the PWM stage is enabled.
How is the maximum duty cycle programmed on UCC28513DWR?
The maximum duty cycle of the PWM stage in UCC28513DWR is programmed via the D_MAX pin (Pin 4): applying a DC voltage between 0.09 V and 0.90 V sets the GT2 duty limit linearly. A typical implementation uses a precision resistor divider from VREF (7.5 V) to ground, yielding ~75% max duty at 4.15 V. Voltages below 0.7 V force 0% duty cycle. This analog control allows fine-tuning to prevent transformer saturation in flyback or forward topologies without firmware changes.
UCC28513DWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Mode:
- Average Current
- Frequency - Switching:
- 200kHz
- Current - Startup:
- 100 µA
- Voltage - Supply:
- 9.7V ~ 18V
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
UCC28513DWR FAQ
1.How can I place an order for UCC28513DWR through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC28513DWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC28513DWR reliable?
The price and inventory of UCC28513DWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC28513DWR is usually 5 days.
3.What payment methods are accepted for UCC28513DWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC28513DWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC28513DWR?
UCC28513DWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC28513DWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC28513DWR?
For technical support, including UCC28513DWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC28513DWR requirements.
6.How does Aetrix verify that UCC28513DWR is sourced from the original manufacturer or authorized distributors?
All UCC28513DWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28513DWR meets industry standards.
7.What is the process for return or replacement of UCC28513DWR?
All UCC28513DWR units undergo pre-shipment inspection (PSI). If there is an issue with UCC28513DWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28513DWR part is unused and in its original packaging.
Return procedure for UCC28513DWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UCC28513DWR Tags
-
ICE2PCS01GXUMA1
Infineon Technologies
-
NCP1654BD133R2G
onsemi
-
MC33262DR2G
onsemi
-
ICE3PCS03GXUMA1
Infineon Technologies
-
NCP1631DR2G
onsemi
-
L4981BD013TR
STMicroelectronics
-
UCC28070DWR
Texas Instruments
-
UCC28070PWR
Texas Instruments
-
UC3854DWTR
Texas Instruments
-
L4981AD013TR
STMicroelectronics
-
UCC2817D
Texas Instruments
-
UC2854BDWTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
