Texas Instruments UCC28516DW
- Part No.:
- UCC28516DW
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
UCC28516DW.pdf
- Description:
- IC PFC CTR AVERAGE 200KHZ 20SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UCC28516DW from Texas Instruments is a dual-stage PFC/PWM combination controller IC for off-line AC-DC power supplies complying with IEC 61000-3-2 harmonic standards. It integrates average-current-mode PFC control and peak-current-mode PWM control in one SOIC-20 package, supports 1:2 PFC:PWM frequency ratio (e.g., 100 kHz PFC / 200 kHz PWM), delivers 2-A source / 3-A sink gate drive on GT1 and GT2, and enables leading-edge PFC + trailing-edge PWM modulation to minimize boost capacitor ripple current - used in industrial and telecom AC-DC front-end designs.
For engineers reviewing the UCC28516DW datasheet, UCC28516DW pinout, UCC28516DW application, or UCC28516DW equivalent, key selection criteria include confirmed 1:2 PFC:PWM frequency ratio, UVLO turn-on at 16 V / turn-off at 9.7 V, PWM UVLO2 turn-off at 3.55 V with 3.2-V hysteresis, soft-start programmability via SS2, and dual high-current gate drivers meeting >100-kHz switching requirements in CCM boost PFC + flyback/buck-derived PWM systems.
Technical Context
The UCC28516DW implements a tightly synchronized dual-loop architecture: its PFC section uses average-current-mode control with input voltage feedforward (VFF), a highly linear three-input multiplier, and transconductance voltage amplifier (gM = 70–130 µS) for fast load transient response; zero-power detect activates below 0.33 V on VAOUT. Its PWM stage employs peak-current-mode control with slope compensation via CT_BUFF, programmable maximum duty cycle (70–80% clamped via D_MAX), and independent UVLO2 (3.55 V turn-off) ensuring staged shutdown during brownout.
Unlike 1:1-ratio variants (e.g., UCC28510), the UCC28516DW fixes PFC frequency at half the PWM oscillator frequency (fPWM = 2 × fPFC), with typical fPWM = 200 kHz and fPFC = 100 kHz when RT = 156 kΩ. Startup sequencing enforces PWM enable only after PFC output reaches 90% of regulation, and disables PWM when PFC output drops to 47% - critical for hold-up time compliance in regulated DC bus applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PFC:PWM Frequency Ratio | 1:2 - PFC operates at half PWM frequency (e.g., 100 kHz PFC / 200 kHz PWM), reducing boost capacitor RMS current vs. 1:1 TEM/TEM schemes. |
| UVLO Turn-On / Turn-Off | 16 V / 9.7 V - Ensures reliable startup above line brownout; hysteresis = 6.3 V prevents chatter during marginal supply conditions. |
| PWM UVLO2 Threshold | 3.55 V turn-off with 3.2-V hysteresis - Enables staged shutdown: PWM ceases while PFC remains active until bulk cap drops to 47% nominal. |
| Gate Drive Capability | 2-A source / 3-A sink on both GT1 (PFC) and GT2 (PWM); 16-ns rise / 7-ns fall into 1-nF load - drives MOSFETs up to ~1 nC gate charge at 200 kHz. |
| Reference Voltage | 7.5-V ±1.5% (over temp); 10-mA output capability - powers external error amplifiers and precision resistor dividers for D_MAX and PKLMT programming. |
| Zero Power Detect Threshold | 0.33 V (falling edge) on VAOUT - forces GT1 disable when PFC output collapses, preventing uncontrolled conduction during no-load or fault conditions. |
| Soft-Start Control | SS2 pin accepts external capacitor; 10.5-µA charge current ramps VERR to 3 V - sets controlled PWM duty ramp time (tSS = 3 V / 10.5 µA × CSS2). |
Pinout & Package
UCC28516DW is housed in a 20-pin SOIC (DW) package with 0.65-mm lead pitch and exposed thermal pad (not electrically connected). Pin layout follows standard TI SOIC-20 footprint; GND (Pin 6) and PWRGND (Pin 11) require separate low-impedance Kelvin connections to minimize ground bounce between analog and power return paths.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GT1 (12) | PFC gate driver output | 2-A source / 3-A sink totem pole; drives PFC switch; disabled if VCC < UVLO threshold or VREF not stable. |
| GT2 (10) | PWM gate driver output | Identical drive strength to GT1; enabled only after PFC output reaches 90% of regulation and UVLO2 is active. |
| VSENSE (3) | PFC voltage feedback input | Inverting input to transconductance amplifier; connects to resistive divider from PFC output; ±120 mV hysteresis enables slew-rate enhancement. |
| VAOUT (1) | PFC voltage amplifier output | Transconductance output (70–130 µS); regulates PFC output; sinks 3.3 mA during over/under-shoot recovery; zero-power detect triggers below 0.33 V. |
| IAC (18) | PFC line voltage sensing input | Current input proportional to rectified line voltage; max 500 µA; feeds multiplier with VFF for input-voltage feedforward. |
| VFF (19) | PFC voltage feedforward output | Sources IAC/2 current; external RC filter generates feedforward voltage (1.4 V at low line, 4.7 V at high line) to linearize multiplier gain. |
| CAOUT (15) | PFC current amplifier output | Wide-bandwidth op-amp output driving PFC PWM comparator; connects to MOUT for loop compensation; swings rail-to-rail (0–5.5 V). |
| ISENSE2 (8) | PWM current sense input | Peak-current-mode input with 1.5-V internal level shift; 1.3–1.65 V threshold; accepts summed oscillator ramp (CT_BUFF) for slope compensation. |
| D_MAX (4) | PWM max duty clamp input | Analog voltage input (0.09–0.90 V range) linearly sets GT2 max duty cycle (70–80%); typically driven by VREF-based resistor divider. |
| SS2 (13) | PWM soft-start timing input | Capacitor-connected node; internal 10.5-µA current charges it to 3 V to ramp VERR and GT2 duty cycle during startup. |
| PKLMT (14) | PFC peak current limit input | Voltage input referenced to 0 V; sets PFC overcurrent threshold via resistor divider from VREF to PFC sense resistor. |
| RT (2) | Oscillator frequency set | Resistor-to-GND sets CT_BUFF frequency (fPWM); 156 kΩ yields ~200 kHz; PFC runs at half that frequency (100 kHz). |
| VREF (20) | Internal 7.5-V reference | Stable 7.5-V ±1.5% output; powers internal circuitry and external bias networks; bypass with 0.1–10 µF ceramic capacitor to GND. |
| GND (6) & PWRGND (11) | Analog & power grounds | GND = signal reference for analog blocks; PWRGND = return path for GT1/GT2 currents; must be joined externally with short, low-inductance trace. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PFC + PWM control | Single-chip solution eliminates inter-controller timing skew, reduces BOM count, and guarantees fixed 1:2 PFC:PWM frequency synchronization for ripple optimization. |
| Leading-edge PFC + trailing-edge PWM modulation | Reduces RMS ripple current in boost output capacitor by up to 30% vs. dual trailing-edge schemes - directly lowers capacitor size, cost, and thermal stress. |
| Programmable PWM maximum duty cycle | D_MAX pin accepts 0.09–0.90 V to set GT2 clamp from 70% to 80%, enabling safe operation in two-transistor forward or flyback topologies with duty-cycle constraints. |
| Enhanced transient response | Transconductance voltage amplifier (gM = 70–130 µS) + slew-rate boost (3.3 mA) recovers PFC output voltage within microseconds during step-load changes. |
| Staged UVLO sequencing | Independent UVLO2 (3.55 V turn-off) ensures PWM shuts down before PFC during brownout, preserving regulated DC bus longer and improving system hold-up time. |
| Zero-power detection | VAOUT < 0.33 V triggers automatic GT1 disable - prevents shoot-through and uncontrolled conduction when PFC output collapses under no-load or fault. |
Applications
| Industrial AC-DC Power Supplies | Telecom Rectifier Modules |
|---|---|
Use Scenario: 300–1000 W industrial power supply with universal AC input (85–265 VAC) feeding isolated DC/DC converters. IC Role / Device Role / Timing Role: UCC28516DW controls CCM boost PFC pre-regulator and flyback PWM stage; provides synchronized 100 kHz / 200 kHz clocking with LEM/TEM modulation. Use Value: Meets IEC 61000-3-2 Class A harmonic limits; reduces boost capacitor RMS current by 25–30%, enabling smaller 105°C-rated electrolytics and extending lifetime. |
Use Scenario: -48 V telecom rectifier with 3–5 kW modular design requiring high efficiency (>90%) and hold-up time ≥20 ms. IC Role / Device Role / Timing Role: UCC28516DW manages PFC output regulation and PWM duty cycle; staged UVLO2 (3.55 V) extends hold-up by keeping PFC active while PWM shuts down early. Use Value: Achieves 47% PFC output drop threshold before PWM disable - increases usable energy from bulk capacitor by ~15% versus fixed 50% cutoff schemes. |
| Medical Equipment Power Front-Ends | Server PSU Auxiliary Rails |
Use Scenario: IEC 60601-1 compliant medical AC-DC converter requiring low EMI, fast transient response, and fault-safe shutdown. IC Role / Device Role / Timing Role: UCC28516DW executes average-current PFC and peak-current PWM control; zero-power detect (0.33 V VAOUT) forces immediate GT1 disable on output collapse. Use Value: Prevents uncontrolled PFC switch conduction during open-feedback faults - eliminates risk of overvoltage on downstream DC/DC inputs. |
Use Scenario: 12 V / 54 A auxiliary rail in 1U server PSU, where space-constrained layout demands minimal component count and thermal management. IC Role / Device Role / Timing Role: UCC28516DW integrates PFC and PWM controllers into one SOIC-20; dual 2-A/3-A gate drivers eliminate external drivers and reduce PCB area. Use Value: Reduces gate driver BOM by 2 ICs and associated passives; SOIC-DW package supports automated assembly and meets IPC Class 2 thermal reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PFC+PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28516N | Same electrical specs and pinout; packaged in 20-pin PDIP (N) instead of SOIC (DW); higher thermal resistance (1 W vs. 0.7 W power dissipation). | Preferred for prototyping or through-hole assembly; unsuitable for high-density SMT production or elevated ambient temperature (>70°C) due to lower power handling. | Select UCC28516N only for breadboarding or legacy through-hole designs; UCC28516DW is standard for volume SMT manufacturing. |
| UCC28070 | Two-phase interleaved CCM PFC controller only - no integrated PWM stage; requires external PWM IC; supports higher power (up to 2 kW) and better THD performance. | Used in high-efficiency server PSUs where interleaving reduces input current ripple and EMI filter size; lacks PWM integration, increasing system complexity. | Choose UCC28070 when >1 kW PFC performance or ultra-low THD is required; UCC28516DW remains optimal for integrated 300–800 W single-stage solutions. |
Compared with UCC28516N, the UCC28516DW offers superior thermal performance in SMT layouts and matches modern assembly requirements; compared with UCC28070, it trades PFC-only optimization for full integration, reducing component count and control-loop latency at the cost of maximum power scalability.
Availability
UCC28516DW is available at Aetrix Electronics and suitable for industrial AC-DC power supplies, telecom rectifier modules, and medical equipment front-ends requiring stable component supply, long-lifecycle support, and IEC 61000-3-2 compliance.
Supply support for UCC28516DW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in power conversion control architectures.
The UCC28516DW belongs to TI's UCC2851x family of combination PFC/PWM controllers, designed specifically for cost-sensitive, space-constrained off-line power supplies needing IEC 61000-3-2 compliance without sacrificing efficiency or reliability.
FAQ
What is the PFC:PWM frequency ratio supported by the UCC28516DW?
The UCC28516DW supports a fixed 1:2 PFC:PWM frequency ratio - meaning the PWM stage operates at twice the frequency of the PFC stage. With RT = 156 kΩ, typical frequencies are 100 kHz for PFC and 200 kHz for PWM. This ratio is hard-coded in silicon and cannot be changed via external components; it distinguishes UCC28516DW from 1:1 variants like UCC28510DW.
How does the UCC28516DW implement staged shutdown during brownout conditions?
The UCC28516DW uses dual UVLO thresholds: main UVLO (16 V on / 9.7 V off) controls chip enable, while dedicated PWM UVLO2 (3.55 V off with 3.2 V hysteresis) governs GT2. During brownout, GT2 disables when PFC output drops to 47% of nominal, but GT1 remains active until the main UVLO threshold is breached - extending hold-up time and maintaining regulated PFC bus longer than single-threshold controllers.
Can the UCC28516DW be used with discontinuous conduction mode (DCM) PFC?
No - the UCC28516DW is explicitly designed for continuous conduction mode (CCM) PFC operation, as confirmed by its average-current-mode control architecture, multiplier-based reference generation, and lack of DCM-specific features (e.g., zero-current detection). Its datasheet specifies CCM as the target operating mode, and using it in DCM risks instability and poor power factor correction.
What is the function of the CT_BUFF pin on the UCC28516DW?
The CT_BUFF pin (Pin 5) outputs a buffered 4-V amplitude PWM oscillator ramp signal. It is designed to drive an external resistor connected to ISENSE2 for slope compensation in peak-current-mode PWM control. Unlike raw oscillator nodes, CT_BUFF provides low-impedance drive (capable of 500 µA) and isolation from internal oscillator loading - ensuring accurate ramp injection without affecting frequency stability.
Does the UCC28516DW support programmable soft-start for the PFC stage?
No - the UCC28516DW provides dedicated soft-start only for the PWM stage via SS2 pin. The PFC stage has no user-programmable soft-start; instead, it relies on inherent loop dynamics and staged enable (PWM waits for PFC output to reach 90% of regulation). This design prioritizes PFC stability and avoids interaction between PFC and PWM startup transients.
UCC28516DW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Mode:
- Average Current
- Frequency - Switching:
- 200kHz
- Current - Startup:
- 100 µA
- Voltage - Supply:
- 9.7V ~ 18V
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
UCC28516DW FAQ
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6.How does Aetrix verify that UCC28516DW is sourced from the original manufacturer or authorized distributors?
All UCC28516DW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28516DW meets industry standards.
7.What is the process for return or replacement of UCC28516DW?
All UCC28516DW units undergo pre-shipment inspection (PSI). If there is an issue with UCC28516DW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28516DW part is unused and in its original packaging.
Return procedure for UCC28516DW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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