Texas Instruments UCC28516N

Overview

UCC28516N from Texas Instruments is a dual-stage combination controller integrating average-current-mode PFC and peak-current-mode PWM control in a single 20-pin PDIP package. It delivers 2-A source / 3-A sink gate drive for both stages, supports 1:2 PFC:PWM frequency ratio (PWM at 2× PFC), and enables IEC 1000-3-2 compliant AC-DC power supplies up to 300 W. Key confirmed parameters: 16 ns GT1 rise time (1 nF load), 7 ns fall time, 7.5-V internal reference, 3.55-V PWM UVLO2 turn-off threshold, and zero-power detect with 0.33-V VAOUT threshold.

For engineers reviewing the UCC28516N datasheet, UCC28516N pinout, UCC28516N application, or UCC28516N equivalent, this page provides verified technical context, validated pin functions, real-world application mappings for boost PFC + flyback PWM systems, and two confirmed alternative parts with documented functional and sequencing differences.

Technical Context

The UCC28516N implements leading-edge modulation for the PFC stage and trailing-edge modulation for the PWM stage to minimize ripple current in the boost output capacitor. Its PFC section uses a three-input linearized multiplier with input voltage feedforward (VFF) and a transconductance voltage amplifier (g_M = 70–130 µS) for fast transient response and accurate power limiting.

The PWM stage features programmable maximum duty cycle (70–80% clamped via D_MAX pin), soft-start (SS2 pin with 10.5 µA charge current), and independent UVLO2 (3.55-V turn-off, 3.2-V hysteresis). Oscillator frequency at CT_BUFF is set by RT resistor; PFC operates at half that frequency (1:2 ratio), confirmed for UCC28516N per Options Table.

Key Specifications

Pinout & Package

UCC28516N is housed in a 20-pin plastic dual in-line package (PDIP-N), with 0.3-inch body width and standard through-hole mounting. Thermal dissipation is rated at 1 W at T_J ≤ 150°C.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC+PWM controller applications.

Compared with UCC28516DW, the UCC28516N offers identical functionality in a through-hole package with higher thermal dissipation (1 W vs. 0.7 W), while UCC28070 lacks integrated PWM and requires external coordination - making UCC28516N optimal for cost-sensitive, medium-power, single-PCB designs.

Availability

UCC28516N is available at Aetrix Electronics and suitable for server power supplies, industrial AC-DC adapters, medical imaging modules, LED drivers, and DIN-rail converters requiring stable component supply and long-term manufacturability.

Supply support for UCC28516N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management ICs and energy-efficient system solutions.

The UCC28516N belongs to TI's UCC2851x family of combination PFC/PWM controllers, designed specifically for cost-optimized, IEC 61000-3-2-compliant AC-DC power supplies in the 100–300-W range.

FAQ

What is the PFC:PWM frequency ratio for UCC28516N?

The UCC28516N is configured for a 1:2 PFC:PWM frequency ratio - meaning the PWM stage operates at twice the frequency of the PFC stage. This is fixed per device option and confirmed in the Available Options table (SLUS517C, p.3). The CT_BUFF pin outputs the PWM frequency; PFC frequency equals half that value. This ratio minimizes boost capacitor ripple and improves hold-up time performance in UCC28516N-based designs.

How does UCC28516N handle startup sequencing between PFC and PWM stages?

The UCC28516N enforces strict built-in sequencing: the PWM stage (GT2) remains disabled until the PFC output voltage reaches 90% of its regulated value, as sensed at VSENSE. This prevents unregulated PWM operation during PFC ramp-up. During line dropout, GT2 stays active until the PFC output falls to 47% of nominal - a behavior specific to UCC28516N and confirmed in the Options table (SLUS517C, p.3).

What is the function of the D_MAX pin on UCC28516N?

The D_MAX pin (Pin 4) on UCC28516N sets the maximum duty cycle for the PWM stage (GT2) via an analog voltage input between 0.09 V and 0.90 V. Within this range, the clamped duty cycle scales linearly from 70% to 80%. It is typically driven by a precision resistor divider from VREF. Voltages below 0.7 V force D_MAX = 0, providing fail-safe shutdown capability - a key safety feature in UCC28516N implementations.

Does UCC28516N include zero-power detection, and how is it implemented?

Yes, UCC28516N includes hardware-based zero-power detection. It monitors the VAOUT pin: when VAOUT falls below 0.33 V (falling edge), the internal comparator disables GT1, halting PFC operation. Hysteresis of 40–140 mV prevents chatter. This feature is confirmed in the Electrical Characteristics table (SLUS517C, p.6) and eliminates no-load power consumption - a verified design advantage in UCC28516N for energy-efficient applications.

What are the absolute maximum ratings for gate drive current on UCC28516N?

UCC28516N specifies pulsed gate drive current limits of −2.5 A (source) and 3.5 A (sink) on both GT1 and GT2 pins. Continuous drive is rated at 0.4 A. These values are absolute maximums per Absolute Maximum Ratings table (SLUS517C, p.3) and define safe operating boundaries - exceeding them risks permanent damage. Real-world designs use series gate resistors (e.g., 2 Ω) to manage overshoot, as recommended in the DETAILED PIN DESCRIPTIONS (SLUS517C, p.9).