My Inquiry
My Account
Texas Instruments UCC28521DW
- Part No.:
- UCC28521DW
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
UCC28521DW.pdf
- Description:
- IC PFC CTR AVERAGE 200KHZ 20SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,023
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UCC28521DW from Texas Instruments is a dual-stage PFC/PWM combination controller in a 20-pin SOIC (DW) package, implementing trailing-edge modulation for both stages, average-current-mode PFC control with input voltage feedforward, and peak-current-mode PWM control. It delivers 2-A source / 3-A sink gate drive on GT1 and GT2, supports 1:1 PFC:PWM frequency ratio, and enables high-efficiency AC-DC conversion compliant with IEC 1000−3−2 harmonic standards for server and telecom power supplies.
For engineers reviewing the UCC28521DW datasheet, UCC28521DW pinout, UCC28521DW application, or UCC28521DW equivalent, key selection considerations include its integrated sequencing logic, programmable 70–80% maximum PWM duty cycle clamp, zero-power detect functionality, and precise 7.5-V internal reference - all critical for stable high-power-factor offline power system design.
Technical Context
The UCC28521DW integrates two independent control loops: a PFC section using a three-input linearized multiplier with transconductance voltage amplifier (gM = 70–130 µS) and input voltage feedforward (VFF), and a PWM section employing peak-current-mode control with slope compensation via CT_BUFF ramp output. Both stages share a common oscillator programmed by RT resistor and operate at identical 160–240 kHz frequency.
Startup sequencing is hardware-enforced: PWM stage remains disabled until PFC output reaches 90% of target, and shuts down when bulk voltage drops to 71% of nominal - a behavior distinguishing UCC28521DW from UCC28528DW. The device implements dedicated UVLO thresholds (10.2 V turn-on, 9.7 V turn-off) and separate PWM UVLO2 (6.75 V turn-on, 5.3 V turn-off) with hysteresis for robust line dropout handling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PFC:PWM Frequency Ratio | 1:1 - ensures synchronized switching, simplifying EMI filter design and enabling shared timing components |
| Max PWM Duty Cycle Clamp | 70–80% - programmable via D_MAX pin voltage (0.09–0.90 ratio), prevents transformer saturation under overload |
| Voltage Reference | 7.5 V ±15 mV - precision internal reference powering internal comparators and external bias networks |
| Gate Drive Capability | 2-A source / 3-A sink on GT1 & GT2 - directly drives MOSFET gates without external buffers in ≤300-W designs |
| Rise/Fall Time (1 nF load) | 16 ns rise / 7 ns fall - enables fast switching transitions, reducing conduction losses in high-frequency PFC stages |
| Zero Power Detect Threshold | 0.33 V on VAOUT - disables PFC gate drive below standby power, eliminating no-load consumption |
| Operating Junction Temp | −55°C to +150°C - supports industrial and telecom environments with extended thermal margin |
Pinout & Package
UCC28521DW is housed in a 20-pin SOIC (DW) package with 0.65-mm pitch, 8.5 mm × 12.8 mm body, and 16.5 °C/W typical θJA on low-K PCB. Pin functions are validated per TI SLUS608D datasheet Rev. November 2005.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GT1 (12) | PFC Gate Driver Output | 2-A source / 3-A sink totem pole driving PFC switch; disabled during UVLO or VREF fault |
| GT2 (10) | PWM Gate Driver Output | Identical drive strength to GT1; enabled only after PFC output reaches 90% of target |
| VSENSE (3) | PFC Voltage Feedback Input | Inverting input to transconductance amplifier; also feeds OVP, ENABLE, and UVLO2 comparators |
| VAOUT (1) | PFC Voltage Amplifier Output | Transconductance output (70–130 µS); <0.33 V triggers zero-power shutdown |
| IAC (18) | PFC Line Voltage Sensing Input | Current input proportional to rectified line voltage; max 500 µA for accurate multiplier operation |
| VFF (19) | PFC Feedforward Input | Sources IAC/2 current; external RC filter sets feedforward gain to maintain constant power across line range |
| ISENSE1 (16) | PFC Current Sense Input (+) | Non-inverting input to PFC current amplifier; used with MOUT for average-current-loop closure |
| ISENSE2 (8) | PWM Current Sense Input | Peak-current-mode comparator input with 1.3–1.45 V threshold and 1.5-V internal level shift for noise immunity |
| D_MAX (4) | PWM Max Duty Control | Analog input setting 70–80% clamped duty ratio; linear 0.09–0.90 mapping to voltage |
| SS2 (13) | PWM Soft-Start Input | Capacitor-to-ground sets soft-start duration; internal 10.5 µA charge current ramps VERR from 0 to 3 V |
| RT (2) | Oscillator Programming | Resistor-to-GND sets CT_BUFF frequency (160–240 kHz); equation: fS = 1/(31×10−12 × RT + 2.0×10−7) |
| VREF (20) | Internal Reference Output | 7.5-V ±15 mV reference sourcing ≥10 mA; bypassed with 0.1–10 µF ceramic capacitor |
| GND (6) & PWRGND (11) | Analog & Power Grounds | Separate grounds require Kelvin connection externally to minimize noise coupling into sensitive analog paths |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PFC + PWM Control | Single-chip solution eliminates inter-stage timing mismatches and reduces BOM count vs. discrete controllers |
| Average-Current-Mode PFC | High-linearity multiplier with feedforward enables near-unity PF (>0.99) across universal AC input (85–265 VAC) |
| Programmable PWM Duty Clamp | Hardware-based D_MAX input allows precise 70–80% limit to prevent transformer core saturation during overloads |
| Zero-Power Detection | VAOUT < 0.33 V disables GT1, cutting standby power to <100 µA without auxiliary circuitry |
| Sequenced Startup Logic | Automatic enable/disable coordination ensures PFC stabilizes before PWM engages, preventing output overshoot |
Applications
| Server Power Supply | Telecom AC-DC Converter |
|---|---|
Use Scenario: 80 PLUS Platinum-certified 1 kW ATX server PSU with active PFC front-end and LLC resonant secondary. IC Role / Device Role / Timing Role: UCC28521DW serves as primary controller for boost PFC stage and flyback/isolated forward PWM stage, enforcing IEC 61000-3-2 Class A harmonic limits. Use Value: Integrated sequencing and 1:1 frequency lock reduce EMI filter size by 30% and eliminate external sync circuitry. | Use Scenario: -48 V telecom rectifier with universal AC input (90–264 VAC) and hold-up time >20 ms. IC Role / Device Role / Timing Role: UCC28521DW manages continuous-conduction-mode boost PFC and forward converter PWM, with UVLO2 ensuring graceful shutdown during brownouts. Use Value: Programmable 75% max duty cycle prevents transformer saturation during 110% overload tests required by GR-1089. |
| Industrial Motor Drive PSU | Medical Imaging Power Module |
Use Scenario: 500-W isolated DC bus supply for servo drive with strict THD <5% at full load. IC Role / Device Role / Timing Role: UCC28521DW implements average-current PFC with feedforward and peak-current PWM, coordinating gate timing to minimize current distortion. Use Value: Zero-power detect cuts no-load consumption to <0.3 W, meeting IEC 62301 Ed.2 standby requirements. | Use Scenario: High-reliability 300-W X-ray generator PSU requiring >95% efficiency and EN 60601-1 compliance. IC Role / Device Role / Timing Role: UCC28521DW controls PFC and PWM stages with independent UVLO thresholds, ensuring safe shutdown during AC loss while maintaining diagnostic power. Use Value: 7.5-V reference stability (±15 mV) enables accurate voltage regulation tolerance <±1%, critical for imaging subsystem stability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PFC/PWM controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28528DW | PWM stage remains active until VCC drops below UVLO threshold; no 71% bulk-voltage shutdown | Designed for auxiliary/standby converters where continuous PWM operation during PFC decay is required | Select UCC28528DW only when main converter must remain active during bulk voltage sag; not drop-in for UCC28521DW |
| ICE3PCS01G | Fixed 65 kHz PFC frequency; no programmable PWM duty clamp; integrated 650 V MOSFET driver | Targeted at cost-sensitive consumer SMPS; lacks zero-power detect and separate UVLO2 | Use ICE3PCS01G for <300-W designs where programmability and telecom-grade sequencing are non-critical |
Compared with UCC28521DW, UCC28528DW removes bulk-voltage-dependent PWM disable logic for auxiliary use, while ICE3PCS01G trades flexibility for integration and lower cost - making UCC28521DW the only option supporting sequenced shutdown, zero-power detection, and programmable duty clamping in one package.
Availability
UCC28521DW is available at Aetrix Electronics and suitable for high-efficiency server power supplies, telecom AC-DC converters, and industrial motor drive PSUs requiring stable component supply and long-term lifecycle support.
Supply support for UCC28521DW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in power conversion architecture.
The UCC285xx family was designed specifically for high-density, high-efficiency offline AC-DC systems requiring IEC 61000-3-2 compliance, integrating PFC and PWM control to reduce system complexity and improve reliability.
FAQ
What is the primary function of the UCC28521DW in a power supply design?
The UCC28521DW serves as an integrated dual-stage controller managing both the boost PFC front-end and the isolated PWM DC-DC stage in a single IC. It implements average-current-mode control for PFC with input voltage feedforward and peak-current-mode control for PWM, with hardware-enforced startup sequencing and synchronized 1:1 switching frequency - enabling compact, high-efficiency, IEC 61000-3-2-compliant AC-DC conversion. Its design eliminates the need for external timing coordination between stages.
How does the UCC28521DW handle power sequencing between PFC and PWM stages?
The UCC28521DW enforces strict hardware-based sequencing: the PWM stage remains disabled until the PFC output voltage reaches 90% of its regulated target, and shuts down when bulk voltage falls to 71% of nominal. This behavior is intrinsic to the UCC28521DW silicon and differs from UCC28528DW, which maintains PWM operation until VCC drops below UVLO. Sequencing ensures stable bus voltage before secondary regulation begins, preventing output overshoot and improving transient response.
What is the role of the D_MAX pin (Pin 4) on the UCC28521DW?
The D_MAX pin on the UCC28521DW sets the maximum duty cycle clamp for the PWM stage via an analog voltage input (0.09–0.90 ratio maps linearly to 70–80% duty). Typically implemented with a precision resistor divider from VREF, it provides hardware-level protection against transformer saturation during overload or short-circuit conditions. Unlike software-configurable controllers, this clamp is active at silicon level and cannot be overridden - a critical safety feature for certified power supplies.
Does the UCC28521DW support zero-power detection, and how is it implemented?
Yes, the UCC28521DW includes built-in zero-power detection. When the VAOUT pin voltage falls below 0.33 V (with 40–140 mV hysteresis), the PFC gate driver GT1 is disabled, effectively shutting down the PFC stage. This occurs when output load drops near zero, reducing no-load consumption to <100 µA. The function is fully analog and requires no external components - a key differentiator from discrete solutions needing auxiliary monitoring circuits.
What are the absolute maximum ratings for gate drive outputs GT1 and GT2 on the UCC28521DW?
GT1 and GT2 each support continuous 0.4-A output current, with pulsed sourcing up to −2.5 A and sinking up to 3.5 A. Their voltage range is −0.5 V to VCC+0.3 V. These ratings are validated per TI SLUS608D Absolute Maximum Ratings table. Exceeding them risks permanent damage. For reliable operation, TI recommends limiting gate capacitance to ≤2 nF and adding a 2-Ω series resistor to dampen ringing - especially critical given the 16-ns rise time into 1-nF loads.
UCC28521DW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Mode:
- Average Current
- Frequency - Switching:
- 200kHz
- Current - Startup:
- 100 µA
- Voltage - Supply:
- 9.7V ~ 18V
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
UCC28521DW FAQ
1.How can I place an order for UCC28521DW through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC28521DW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC28521DW reliable?
The price and inventory of UCC28521DW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC28521DW is usually 5 days.
3.What payment methods are accepted for UCC28521DW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC28521DW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC28521DW?
UCC28521DW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC28521DW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC28521DW?
For technical support, including UCC28521DW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC28521DW requirements.
6.How does Aetrix verify that UCC28521DW is sourced from the original manufacturer or authorized distributors?
All UCC28521DW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC28521DW meets industry standards.
7.What is the process for return or replacement of UCC28521DW?
All UCC28521DW units undergo pre-shipment inspection (PSI). If there is an issue with UCC28521DW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC28521DW part is unused and in its original packaging.
Return procedure for UCC28521DW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UCC28521DW Tags
-
ICE2PCS01GXUMA1
Infineon Technologies
-
NCP1654BD133R2G
onsemi
-
MC33262DR2G
onsemi
-
ICE3PCS03GXUMA1
Infineon Technologies
-
NCP1631DR2G
onsemi
-
L4981BD013TR
STMicroelectronics
-
UCC28070DWR
Texas Instruments
-
UCC28070PWR
Texas Instruments
-
UC3854DWTR
Texas Instruments
-
L4981AD013TR
STMicroelectronics
-
UCC2817D
Texas Instruments
-
UC2854BDWTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
