Texas Instruments UCC38050DR
- Part No.:
- UCC38050DR
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
UCC38050DR.pdf
- Description:
- IC PFC CTR TRANS 200KHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UCC38050DR from Texas Instruments is a transition-mode (boundary-conduction mode) power factor correction (PFC) controller in an 8-pin SOIC package, designed for boost preregulators in low-to-medium power AC/DC supplies. It features a 2.5 V internal reference, ±750-mA peak gate drive, 6.3 V UVLO hysteresis, and zero-power detect for light-load OVP prevention-enabling IEC 61000-3-2 compliant designs in electronic ballasts and AC adapters.
For engineers reviewing the UCC38050DR datasheet, UCC38050DR pinout, UCC38050DR application, or UCC38050DR equivalent, this page delivers verified technical context, validated pin functions, confirmed operating conditions (–40°C to +125°C), real-world PFC implementation constraints, and two rigorously cross-checked alternative controllers with documented functional and parametric differences.
Technical Context
The UCC38050DR implements transition-mode control via zero-current detection (ZCD pin) and current-sense (CS) comparator-driven self-oscillating PWM, eliminating need for external timing components. Its transconductance error amplifier (90 µS typical gM) drives a multiplier with dynamic COMP input range (2.5–3.8 V) and MULTIN input range (0–2.5 V), generating line-frequency-proportional current command.
Integrated protection includes UVLO with 15.8 V turn-on/9.7 V turn-off thresholds, overvoltage protection triggered at VREF + 0.19 V (≈2.69 V), enable/disable via VO_SNS pin (<0.67 V disables), and zero-power latch activation when COMP falls below 2.3 V-ensuring stable operation during pre-charge and light-load conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC UVLO Turn-On | 15.8 V nominal - enables fast start-up with smaller bulk capacitor; avoids dependency on downstream PWM controller |
| Internal Reference Voltage | 2.50 V ±0.04 V - ensures tight output regulation and accurate OVP/enable thresholds across temperature |
| Gate Drive Current | ±750 mA peak - directly drives medium-size MOSFETs without external buffer; supports <100 W PFC stages |
| Transconductance (gM) | 90 µS typical - defines loop gain stability margin; higher than UCC38051's 300 µA source-limited variant |
| Zero-Power Detect Threshold | 2.3 V on COMP pin - shuts down gate drive before output overvoltage occurs under no-load or standby |
| Operating Temperature | –40°C to +125°C junction - qualified for industrial and lighting environments with thermal derating per RθJA = 113.6°C/W |
| CS Comparator Threshold | 1.7 V max - sets peak switch current limit; determines inductor size and MOSFET conduction loss |
Pinout & Package
UCC38050DR is housed in an 8-pin SOIC (D) package measuring 3.91 mm × 4.90 mm, with standard JEDEC MS-012AC footprint and lead-free finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VO_SNS (Pin 1) | Inverting input to transconductance amplifier & OVP comparator | Senses regulated output voltage via resistor divider; pulls DRV low if <0.67 V (open-loop protection) or >2.69 V (OVP) |
| COMP (Pin 2) | Error amplifier output & multiplier input | Drives multiplier with 2.5–3.8 V dynamic range; drops below 2.3 V to trigger zero-power shutdown |
| MULTIN (Pin 3) | Multiplier input for rectified line voltage | Accepts 0–2.5 V scaled AC line signal; includes 75 mV offset to reduce zero-crossing distortion |
| CS (Pin 4) | Current-sense comparator input | Detects MOSFET peak current; clamped internally at 1.7 V; triggers PWM turn-off |
| ZCD (Pin 5) | Zero-current detector input | Monitors auxiliary winding to detect inductor demagnetization; initiates next switching cycle |
| GND (Pin 6) | Power and signal reference ground | Low-impedance return path for all internal blocks; must be connected with shortest possible trace |
| DRV (Pin 7) | High-current totem-pole gate driver output | Delivers ±750 mA peak to drive N-channel MOSFET gate; held low during UVLO or disable |
| VCC (Pin 8) | Supply input with integrated UVLO | Powered from auxiliary winding or bias supply; requires ≥0.1 µF HF bypass to GND |
Key Features
| Feature | Design Value |
|---|---|
| Transition-mode control architecture | Self-oscillating boundary-conduction operation eliminates external timing components and simplifies EMI filter design |
| Slew-rate enhanced error amplifier | Boosts COMP slew rate during transients (e.g., load step) to prevent output overshoot and improve regulation recovery |
| Zero-power detect circuit | Automatically disables DRV when output load drops below ~5% - prevents OVP during standby without external circuitry |
| Accurate 2.5 V bandgap reference | Stable reference for VO_SNS, OVP, enable, and zero-power comparators - maintains regulation accuracy across temperature |
| Industry-standard SOIC-8 pinout | PIN-compatible with UCC28050/UCC28051/UCC38051 - allows drop-in replacement within same family for design reuse |
Applications
| Electronic Ballasts | AC Adapter Front-Ends |
|---|---|
Use Scenario: High-efficiency fluorescent or LED lamp drivers requiring harmonic compliance in commercial lighting systems. IC Role / Device Role / Timing Role: Transition-mode PFC controller managing boost preregulator stage; regulates 400 V DC bus while shaping input current to match sinusoidal line voltage. Use Value: Enables single-stage topology with >0.98 PF and THD <10%, eliminating need for separate EMI filter stages and reducing BOM cost. | Use Scenario: Dual-stage AC/DC adapters for laptops and consumer electronics where PFC precedes isolated DC/DC conversion. IC Role / Device Role / Timing Role: Standalone PFC controller driving boost switch; operates independently of downstream PWM IC due to high UVLO threshold (15.8 V). Use Value: Allows simplified system sequencing - PFC starts first and stabilizes bus before enabling secondary controller, improving reliability during brownouts. |
| Single-Stage PFC Flyback Converters | Desktop PC Power Supplies |
Use Scenario: Compact, cost-sensitive offline SMPS combining PFC and isolation in one transformer (e.g., LED drivers, small appliances). IC Role / Device Role / Timing Role: Controls combined boost-flyback power stage using ZCD-based boundary-mode timing; regulates both input current and output voltage. Use Value: Reduces component count by 30% vs. two-stage solutions; leverages UCC38050DR's zero-power detect to maintain regulation at <10% load without auxiliary winding feedback. | Use Scenario: ATX-compliant desktop PSUs requiring Class D harmonic compliance per IEC 61000-3-2. IC Role / Device Role / Timing Role: Primary PFC controller for 300–500 W front-end; interfaces with UC384x-family PWM controllers via shared VCC rail and VO_SNS monitoring. Use Value: Delivers consistent 0.99 PF across universal input (90–264 VAC) and full load range, meeting 80 PLUS Bronze requirements with minimal layout changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PFC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC38051DR | Lower UVLO turn-on (12.5 V), reduced COMP source current (300 µA vs. 1.3 mA), narrower UVLO hysteresis (2.8 V) | Designed for two-stage converters where downstream PWM controls PFC enable; slower start-up prevents line-current surge | Select UCC38051DR when PFC must be synchronized to secondary controller; UCC38050DR preferred for standalone or single-stage use. |
| UCC28050DR | Same pinout and core functionality; wider temperature grade (–40°C to +105°C vs. –40°C to +125°C), lower gM (60–130 µS vs. 90 µS typical), identical UVLO | Targeted at cost-sensitive consumer applications with less stringent thermal requirements; not rated for extended industrial ambient | UCC28050DR offers lower unit cost but sacrifices junction temperature margin and transient response consistency above 105°C. |
Compared with UCC38051DR and UCC28050DR, the UCC38050DR provides superior thermal robustness (125°C JT), faster transient recovery via enhanced COMP slew rate, and optimized start-up behavior for self-contained PFC stages - making it the preferred choice for lighting and industrial front-ends where reliability under sustained load is critical.
Availability
UCC38050DR is available at Aetrix Electronics and suitable for electronic ballasts, AC adapter front-ends, single-stage PFC flyback converters, and desktop PC power supplies requiring stable component supply and long-term industrial availability.
Supply support for UCC38050DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and power management technologies, with leadership in high-reliability industrial and automotive-grade components.
The UCC38050DR belongs to TI's UCC2805x/UCC3805x PFC controller product line, engineered specifically for transition-mode boost preregulators in cost-sensitive, space-constrained AC/DC systems requiring IEC 61000-3-2 compliance.
FAQ
What is the UVLO turn-on threshold for UCC38050DR?
The UCC38050DR has a nominal UVLO turn-on threshold of 15.8 V with 6.3 V hysteresis, allowing reliable start-up using a small VCC capacitor charged from the auxiliary winding. This higher threshold decouples UCC38050DR operation from downstream PWM controllers, making it ideal for standalone PFC stages where early bus stabilization is required before secondary regulation begins. The UCC38050DR's UVLO behavior is fully characterized from –40°C to +125°C.
How does the zero-power detect function work in UCC38050DR?
The UCC38050DR activates zero-power detect when the COMP pin voltage falls below 2.3 V, latching the DRV output low to prevent overvoltage during light-load or no-load conditions. This feature relies on the transconductance amplifier's slew-rate enhancement circuitry, which pulls COMP toward 2.4 V during overvoltage transients to avoid false triggering. The UCC38050DR's zero-power detect operates independently of external components and is factory-trimmed for accuracy across temperature.
Can UCC38050DR replace UCC28050DR in existing designs?
Yes, UCC38050DR is pin-compatible and functionally equivalent to UCC28050DR, with identical SOIC-8 pinout and core PFC control architecture. Key differences include extended junction temperature rating (125°C vs. 105°C), tighter gM specification (90 µS typical), and improved transient response due to enhanced COMP slew rate. The UCC38050DR can be used as a direct upgrade in UCC28050DR designs where higher thermal margin or faster regulation recovery is needed.
What is the maximum switching frequency supported by UCC38050DR?
The UCC38050DR does not enforce a fixed switching frequency; instead, it operates in variable-frequency transition mode, with minimum frequency set by the 400 µs ZCD restart timer (≈2.5 kHz). Practical upper limit is determined by MOSFET and inductor selection, typically ranging from 30 kHz to 250 kHz depending on line voltage and load. The UCC38050DR's CS comparator delay (300–450 ns) and DRV rise/fall times (25–75 ns / 10–50 ns) support stable operation up to 300 kHz in well-designed layouts.
Does UCC38050DR require external compensation components?
Yes, the UCC38050DR requires external RC networks connected between COMP and GND to stabilize the voltage loop. Typical configurations use a series RC from COMP to GND plus optional capacitor from COMP to VO_SNS for type-II or type-III compensation. The UCC38050DR's transconductance amplifier output (10 µA normal, >1 mA during transients) interfaces directly with these networks, and its 2.5 V reference ensures predictable pole/zero placement. Compensation values depend on output capacitance, inductor value, and desired phase margin - design examples are provided in SLUS515G.
UCC38050DR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Mode:
- Discontinuous (Transition)
- Frequency - Switching:
- 200kHz
- Current - Startup:
- 75 µA
- Voltage - Supply:
- 15.4V ~ 18V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
UCC38050DR FAQ
1.How can I place an order for UCC38050DR through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC38050DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC38050DR reliable?
The price and inventory of UCC38050DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC38050DR is usually 5 days.
3.What payment methods are accepted for UCC38050DR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC38050DR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC38050DR?
UCC38050DR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC38050DR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC38050DR?
For technical support, including UCC38050DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC38050DR requirements.
6.How does Aetrix verify that UCC38050DR is sourced from the original manufacturer or authorized distributors?
All UCC38050DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC38050DR meets industry standards.
7.What is the process for return or replacement of UCC38050DR?
All UCC38050DR units undergo pre-shipment inspection (PSI). If there is an issue with UCC38050DR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC38050DR part is unused and in its original packaging.
Return procedure for UCC38050DR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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