Texas Instruments UCC38051DR

Overview

UCC38051DR from Texas Instruments is a transition-mode (boundary-conduction mode) power factor correction (PFC) controller designed for boost preregulators in low-to-medium power AC-DC systems. It features a 2.5 V internal reference, ±750-mA peak gate drive, 12.5 V UVLO turn-on threshold, and zero-power detect for light-load OVP prevention - enabling compliant IEC 61000-3-2 designs in AC adapters and two-stage SMPS.

For engineers reviewing the UCC38051DR datasheet, UCC38051DR pinout, UCC38051DR application, or UCC38051DR equivalent, key selection criteria include its narrow 2.8 V UVLO hysteresis, 300 µA g_M amplifier source current for controlled start-up, ZCD-based self-oscillating timing, and compatibility with external MOSFETs in critical conduction mode PFC stages.

Technical Context

The UCC38051DR implements transition-mode control via zero-current detection (ZCD pin) to trigger switch turn-on and current-sense (CS pin) comparison to terminate each cycle - eliminating need for external clock or ramp generation. Its transconductance error amplifier (90 µS typical g_M) drives a multiplier block that generates line-frequency proportional current command using VMULTIN and COMP inputs.

UVLO is set at 12.5 V turn-on / 9.7 V turn-off (2.8 V hysteresis), enabling synchronization with downstream PWM controllers in two-stage converters. The zero-power detect circuit disables gate drive when COMP falls below 2.3 V, preventing output overvoltage during no-load or light-load conditions without auxiliary sensing.

Key Specifications

Pinout & Package

UCC38051DR is housed in an 8-pin SOIC (D package), 3.91 mm × 4.90 mm body size, with GND-referenced layout optimized for noise immunity in high-dV/dt PFC stages.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar transition-mode PFC controller applications.

Compared with UCC38050DR, UCC38051DR trades faster start-up for tighter upstream control; compared with L6562ADTR, it integrates zero-power detect and OVP, reducing BOM count and improving light-load reliability without external components.

Availability

UCC38051DR is available at Aetrix Electronics and suitable for AC adapter front-ends, two-stage desktop SMPS, and lighting ballast PFC stages requiring stable component supply, long-term lifecycle support, and TI-qualified manufacturing traceability.

Supply support for UCC38051DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in power management ICs and industrial-grade reliability.

The UCC38051DR belongs to TI's UCC3805x family of transition-mode PFC controllers, engineered specifically for cost-effective, IEC 61000-3-2-compliant boost preregulators in two-stage AC-DC conversion architectures.

FAQ

What is the UVLO behavior of the UCC38051DR and how does it differ from UCC38050DR?

The UCC38051DR has a 12.5 V turn-on threshold and 9.7 V turn-off threshold, yielding a 2.8 V hysteresis - optimized for coordination with downstream PWM controllers. In contrast, UCC38050DR uses 15.8 V turn-on and 9.7 V turn-off (6.3 V hysteresis) for standalone operation. This difference means UCC38051DR starts only after the system's main controller asserts sufficient VCC, preventing premature PFC activation. The UCC38051DR's lower threshold also allows smaller hold-up capacitors on the VCC rail.

How does the zero-power detect function work in the UCC38051DR?

The UCC38051DR monitors the COMP pin voltage and activates zero-power detect when it falls below 2.3 V - indicating near-zero load current. This latches the DRV output low, halting switching and preventing output overvoltage. Unlike basic disable functions, this is an autonomous analog comparator action tied directly to the g_M amplifier's output state, requiring no external circuitry. It operates independently of VO_SNS feedback integrity, making it effective even during open-loop faults.

Can the UCC38051DR be used in continuous conduction mode (CCM) PFC designs?

No - the UCC38051DR is architecturally designed exclusively for transition-mode (boundary-conduction mode) operation. Its timing relies on ZCD detection of inductor zero-current crossings and self-oscillating PWM logic; it lacks the error amplifier compensation structure, ramp injection, or fixed-frequency clock required for CCM control. Attempting CCM use results in unstable frequency, poor THD, and potential overcurrent failure. For CCM, TI recommends UCC28070 or similar dedicated CCM controllers.

What is the role of the MULTIN pin and how should it be biased in the UCC38051DR?

The MULTIN pin (Pin 3) accepts a scaled version of the rectified AC line voltage - typically 0–2.5 V - and serves as one input to the internal analog multiplier. It must be driven through a resistive divider from the boost diode cathode or bridge output. The UCC38051DR applies a built-in 75 mV offset to this signal to minimize zero-crossing distortion and improve THD performance. Exceeding 2.5 V risks violating ABS MAX ratings; values below 0.5 V degrade line-current shaping accuracy.

Does the UCC38051DR require external components for OVP, or is it fully integrated?

The UCC38051DR integrates dual-layer OVP: first, slew-rate enhancement in the g_M amplifier pulls COMP low when VO_SNS exceeds ~105% of VREF, suppressing multiplier output; second, a dedicated OVP comparator trips at VO_SNS = VREF + 0.18 V (≈2.68 V), forcing DRV low until VO_SNS falls below VREF. No external components are required - the VO_SNS resistor divider sets both regulation and OVP thresholds simultaneously. This eliminates need for separate voltage monitors or comparators.