Texas Instruments UCC38500DW

Overview

UCC38500DW from Texas Instruments is a dual-stage active power factor correction (PFC) and DC-DC controller IC integrating average-current-mode PFC control with peak-current-mode downstream PWM control. It delivers near-unity power factor, programmable 80–120 kHz oscillator frequency, 7.5 V internal reference, and synchronized leading-edge (PFC) / trailing-edge (DC-DC) modulation for reduced bulk-capacitor ripple. Used in universal-input AC-DC power supplies such as server PSUs and industrial power modules.

For engineers reviewing the UCC38500DW datasheet, UCC38500DW pinout, UCC38500DW application, or UCC38500DW equivalent, key selection criteria include its 16.5 V/10 V UVLO threshold, dual-gate drivers (GT1/GT2) with 5–12 Ω pull-up resistance, 0°C to 70°C operating temperature range, and DW package compatibility with tape-and-reel delivery (UCC38500DWTR).

Technical Context

The UCC38500DW implements a two-stage control architecture: the PFC section uses average current-mode control with line-voltage feedforward (VFF) derived from IAC mirroring, while the second stage employs peak-current-mode control with external error feedback via VERR. Its multiplier-based current shaping ensures low THD across 85–265 V_RMS input.

Internal functions include programmable soft-start (SS2), zero-power detection (0.175–0.5 V VAOUT threshold), overvoltage protection (OVP/ENBL window comparator), and independent UVLO2 for the PWM stage (6.3–7.3 V turn-on, 0.96–1.44 V hysteresis). The device supports continuous conduction mode (CCM) boost PFC followed by isolated forward or flyback DC-DC topologies.

Key Specifications

Pinout & Package

The UCC38500DW is housed in a 20-pin SOIC (DW) package with exposed thermal pad, rated for surface-mount reflow assembly and tape-and-reel handling (UCC38500DWTR). Pin assignments are identical to the N-package variant per TI SLUS419C.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-stage PFC + DC-DC controller applications.

Compared with UCC28500DW, the UCC38500DW trades extended temperature range for lower-cost commercial qualification; compared with UCC38502DW, it provides tighter UVLO2 hysteresis (0.96–1.44 V) for faster PWM disable during marginal PFC output conditions.

Availability

UCC38500DW is available at Aetrix Electronics and suitable for server power supplies, industrial AC-DC modules, medical equipment PSUs, and test & measurement instruments requiring stable component supply and long-term production continuity.

Supply support for UCC38500DW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management IC design.

The UCC38500DW belongs to TI's UCC2850x/UCC3850x family of integrated PFC + DC-DC controllers, engineered specifically for cost-sensitive, high-efficiency two-stage AC-DC power conversion in commercial and light-industrial applications.

FAQ

What is the recommended gate resistor value for GT1 on the UCC38500DW?

The UCC38500DW datasheet specifies a minimum series gate resistor of 10.5 Ω for GT1 to prevent overshoot when driving capacitive MOSFET gates. This value is derived from stability analysis in Figure 4 of SLUS419C and assumes typical VCC and load conditions. Lower values risk ringing and shoot-through; higher values increase switching losses. For the UCC38500DW, use 12 Ω as a robust default unless layout parasitics are minimized.

Does the UCC38500DW support voltage-mode control for the second-stage DC-DC converter?

Yes, the UCC38500DW supports both voltage-mode and current-mode control for the second stage. For voltage-mode operation, feed the CT oscillator ramp through a voltage divider into the ISENSE2 pin instead of using a current-sense resistor. This configuration bypasses peak-current limiting but retains soft-start and UVLO2 protection. The UCC38500DW's flexible ISENSE2 input allows either method without hardware changes.

How does the UCC38500DW implement line voltage feedforward (VFF)?

The UCC38500DW generates VFF by mirroring half the IAC current into an external RC filter at the VFF pin. This produces a DC voltage proportional to RMS line voltage - 1.4 V at low line and ~4.7 V at high line - which scales the multiplier gain to maintain constant input power. Unlike resistor-divider feedforward, this method avoids high-voltage components and achieves better accuracy across 85–265 V_RMS, as confirmed in Figure 3 of SLUS419C.

What is the function of the OVP/ENBL pin on the UCC38500DW?

The OVP/ENBL pin on the UCC38500DW is a dual-function window comparator input. When pulled above VREF + 0.5 V (≈8.0 V), it disables only the PFC gate driver (GT1). When pulled below 1.7–2.1 V, it disables both GT1 and GT2 and resets the SS2 soft-start capacitor. This pin also defines the active range of the second-stage PWM, enabling coordinated start-up and fault shutdown without external logic.

Can the UCC38500DW operate with a 50% duty cycle limit on GT2 for transformer reset?

Yes, the UCC38500DW enforces a hard 50% maximum duty cycle on GT2 via internal clamping of the VERR signal at 4.5 V. This ensures sufficient off-time for magnetic reset in forward or push-pull topologies. The clamp operates independently of external feedback and remains active across all operating conditions, including during soft-start and overload recovery - a core design feature verified in the "second stage duty cycle clamp" specification table of SLUS419C.