Texas Instruments UCC38500N
- Part No.:
- UCC38500N
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 20-DIP (0.300", 7.62mm)
- Datasheet:
-
UCC38500N.pdf
- Description:
- IC PFC CTR AV CURR 100KHZ 20DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,048
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UCC38500N from Texas Instruments is a dual-stage power factor correction (PFC) and DC-DC controller IC integrating average-current-mode PFC control with peak-current-mode downstream PWM control in a single 20-pin PDIP package. It delivers near-unity power factor, programmable 100 kHz oscillator, leading-edge PFC + trailing-edge synchronized second-stage modulation, and supports universal AC input (85–265 VRMS) for offline 100-W boost-forward converters.
For engineers reviewing the UCC38500N datasheet, UCC38500N pinout, UCC38500N application, or UCC38500N equivalent, this controller enables coordinated start-up sequencing, feedforward line regulation, accurate power limiting, and zero-power detection - critical for high-efficiency, low-ripple AC-DC front-end designs meeting IEC 61000-3-2 Class D compliance.
Technical Context
The UCC38500N implements a two-stage control architecture: its PFC section uses average current-mode control with a high-linearity analog multiplier (IAC input), voltage amplifier (7.5-V reference), and noise-attenuated current amplifier to shape line current; the second stage employs external error feedback via VERR and peak-current sensing on ISENSE2 with 50% duty-cycle clamping and programmable soft-start (SS2).
It features dual UVLO thresholds: wide-range 16.5 V/10 V turn-on/off for bootstrap bias operation and a second-stage UVLO2 with 6.75 V turn-on and 1.2 V hysteresis (UCC38500-specific), enabling reliable start-up only after PFC output reaches ≥74% of nominal bulk voltage - preventing overstress during brownout conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Oscillator Frequency | 100 kHz typical (80–120 kHz total variation); sets switching timing for both PFC and DC-DC stages with RT/CT programming. |
| Voltage Reference | 7.5 V ±12 mV (0°C to 70°C); stable internal reference used for error amplifiers, OVP threshold, and PKLMT level-shifting. |
| PFC Gate Driver (GT1) | 100 mA sink / 200 mA source; totem-pole output with 2–12 Ω pull-down/pull-up resistance for direct MOSFET drive without external buffers. |
| Second-Stage Gate Driver (GT2) | 100 mA sink / 200 mA source; limited to ≤50% duty cycle to ensure transformer reset in forward/isolated topologies. |
| UVLO Thresholds | VCC turn-on: 16.0 V (±0.6 V), hysteresis: 6.3 V; UVLO2 turn-on: 6.75 V (±0.45 V) - ensures staged, sequenced power-up. |
| Zero-Power Detection | 0.33 V threshold on VAOUT; disables PFC output when boost output falls below regulation, reducing no-load consumption. |
| Input Voltage Feedforward (VFF) | Generates RMS-proportional signal (1.4 V at low line, 4.7 V at high line) using mirrored IAC current and external RC filter - eliminates high-voltage sensing components. |
Pinout & Package
UCC38500N is housed in a 20-pin plastic DIP (N) package with 0.3-inch width, lead spacing of 0.1 inches, and operating junction temperature range of 0°C to 70°C. Pin assignments are identical between N and DW packages per TI SLUS419C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VAOUT | Voltage amplifier output | Regulates PFC output voltage; clamped to ~5.5 V internally; feeds multiplier and enables zero-power shutdown at ≤0.33 V. |
| RT | Oscillator charging current input | Sets oscillator frequency with CT; 22 kΩ recommended for 100 kHz; nominal 3 V bias. |
| VSENSE | PFC voltage error amplifier inverting input | Connects to output divider network; forms compensation loop with CAOUT-MOUT. |
| OVP/ENBL | PFC overvoltage/enable control | Window comparator: disables GT1 if boost exceeds +6.67%, disables both GT1/GT2 and resets SS2 if pulled below 1.9 V. |
| CT | Oscillator timing capacitor node | Capacitor to GND sets frequency per f = 0.725/(RT × CT); requires short, low-inductance GND path. |
| GND | Analog ground reference | Reference for all voltages; bypass VCC/VREF directly here with ≥0.1 µF ceramic capacitor. |
| VERR | Second-stage voltage error input | Accepts opto-coupled secondary-side error signal; internal 4.5 V clamp limits GT2 duty cycle to ≤50%. |
| ISENSE2 | Second-stage peak current sense input | Receives current-sense resistor voltage + optional CT ramp for slope compensation; comparator threshold = 1.05 V. |
| VCC | Positive supply input | 12–17 V operation; requires ≥20 mA supply; inhibited until UVLO threshold exceeded; bypassed to GND. |
| GT2 | Second-stage gate driver output | Drives downstream PWM switch (e.g., forward converter MOSFET); duty cycle hard-clamped to 50% max. |
| VREF | 7.5 V precision reference output | Supplies 10 mA; disabled below UVLO; used for PKLMT level-shifting and peripheral biasing; bypass to GND required. |
| VFF | RMS feedforward voltage output | Generated by mirroring IAC; scaled to 1.4 V (low line) or 4.7 V (high line); enables constant input power across 3:1 AC range. |
| IAC | AC line current input | Current-mode input to multiplier (max 500 µA); primary source for distortion-free line voltage sensing and feedforward. |
| MOUT | Multiplier output / current amp inverting input | High-impedance node connecting multiplier current output and CAOUT feedback; used for loop compensation. |
| ISENSE1 | PFC current sense non-inverting input | Connects to boost inductor sense resistor; works down to GND; paired with MOUT for differential current amplification. |
| CAOUT | Current amplifier output | Drives PFC PWM latch; swings rail-to-rail; enables zero-duty-cycle capability for full load regulation. |
| PKLMT | PFC peak current limit threshold | 0 V reference; use resistor divider from sense resistor to VREF to set overcurrent trip point. |
| SS2 | Second-stage soft-start capacitor node | Charges externally with –10 µA current; controls PWM ramp-up; rapidly discharges on disable or UVLO2 dropout. |
| GT1 | PFC gate driver output | Drives boost switch MOSFET; supports >95% duty cycle; requires ≥10.5 Ω series gate resistor to prevent overshoot. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual-stage control | Single-chip solution replaces discrete PFC + PWM controllers - reduces BOM count, layout area, and timing skew between stages. |
| Leading-edge PFC + trailing-edge PWM synchronization | Minimizes overlap conduction between boost and DC-DC switches, cutting bulk-capacitor ripple current and EMI generation. |
| Programmable feedforward (VFF) | Eliminates need for high-voltage resistive dividers; uses low-voltage IAC mirroring and simple RC filter for robust RMS line sensing. |
| Coordinated start-up sequencing | Second stage remains disabled until PFC output reaches ≥74% of nominal; prevents inrush stress and unregulated operation. |
| Accurate power limiting | Multiplies IAC × VFF² to derive instantaneous line power; enables precise over-power protection independent of line voltage. |
| Zero-power detection | Monitors VAOUT to detect loss of PFC regulation; shuts down GT1 to eliminate standby losses when output collapses. |
Applications
| Industrial Power Supplies | Medical AC-DC Adapters |
|---|---|
|
Use Scenario: 100-W offline power supply for PLC I/O modules operating from 85–265 VRMS with 12 V/10 A output and 16 ms hold-up time. IC Role / Device Role / Timing Role: UCC38500N serves as the integrated PFC + forward converter controller, managing boost inductor current shaping, bulk voltage regulation, and isolated secondary-side error feedback coordination. Use Value: Achieves >0.99 power factor and <15% THD at full load while eliminating external line-sensing components and ensuring safe, sequenced start-up under brownout. |
Use Scenario: Compact, low-noise AC-DC adapter for portable diagnostic equipment requiring IEC 60601-1 compliance and low EMI emissions. IC Role / Device Role / Timing Role: UCC38500N implements continuous-conduction-mode boost PFC followed by current-mode forward conversion with opto-isolated VERR feedback. Use Value: Synchronized leading/trailing-edge modulation reduces output capacitor ripple current by >30%, lowering thermal stress and enabling smaller, longer-life electrolytics. |
| LED Driver Front-Ends | Server PSU Auxiliary Rails |
|
Use Scenario: Constant-power LED driver for commercial lighting with universal input, 385 V bulk bus, and 48 V/2 A output. IC Role / Device Role / Timing Role: UCC38500N regulates boost output to fixed 385 V, then controls downstream buck-derived stage via VERR; PKLMT enforces strict input power limit. Use Value: Accurate IAC × VFF²-based power limiting maintains constant LED power across line variations - critical for lumen consistency and thermal management. |
Use Scenario: Auxiliary 5 V/3 A rail in 1U server PSU, powered from main 385 V bulk bus with tight transient response and fault containment. IC Role / Device Role / Timing Role: UCC38500N manages PFC stage and drives synchronous rectified forward converter; OVP/ENBL provides fast bulk overvoltage shutdown. Use Value: Dual UVLO (VCC + UVLO2) ensures auxiliary rail only activates after main PFC stabilizes - preventing cascading faults during cold start or line sag. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-stage PFC + DC-DC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28500N | Identical pinout and function but rated for –40°C to 85°C; UVLO2 threshold is 6.75 V with 1.2 V hysteresis (same as UCC38500N), but VCC UVLO is 16.5 V/10 V with 6.3 V hysteresis - identical turn-on behavior. | Supports wider industrial temperature range; suitable where ambient exceeds 70°C or storage below 0°C is required. | Select UCC28500N for extended temperature operation; UCC38500N is optimized for cost-sensitive commercial applications with 0°C to 70°C requirement. |
| UCC38502N | Different UVLO2 profile: same 6.75 V turn-on but 3.0 V hysteresis (vs. 1.2 V), enabling second-stage operation down to 50% of nominal bulk voltage (vs. 74% for UCC38500N). | Enables deeper brownout ride-through; appropriate for systems requiring sustained operation during severe line sags. | Choose UCC38502N only if system must maintain DC-DC output during prolonged low-line events; UCC38500N prioritizes reliability via earlier shutdown. |
Compared with UCC28500N, UCC38500N trades extended temperature rating for lower cost and identical functional performance in commercial environments; compared with UCC38502N, it provides tighter UVLO2 hysteresis for more conservative second-stage enablement - improving system robustness against marginal PFC regulation.
Availability
UCC38500N is available at Aetrix Electronics and suitable for industrial power supplies, medical AC-DC adapters, LED driver front-ends, and server auxiliary rails requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for UCC38500N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.
The UCC38500N belongs to TI's UCC2850x family of integrated PFC + DC-DC controllers, designed specifically for cost-effective, high-efficiency offline AC-DC power supplies targeting IEC 61000-3-2 compliance and simplified system-level design.
FAQ
What is the operating temperature range for the UCC38500N?
The UCC38500N is specified for an operating junction temperature range of 0°C to 70°C, as confirmed in the "AVAILABLE OPTIONS" table of TI SLUS419C. This distinguishes it from the UCC28500N (–40°C to 85°C) and aligns with commercial-grade power supply requirements. The device's absolute maximum junction temperature is 125°C, and storage temperature spans –65°C to 150°C.
How does the UCC38500N implement power factor correction?
The UCC38500N achieves near-unity power factor using average current-mode control: it senses instantaneous line current via the IAC pin, shapes the PFC switch duty cycle using a high-linearity analog multiplier (IAC × VFF²), and regulates output voltage through the VAOUT/VSENSE loop. This forces input current to track input voltage waveform with <15% THD at full load per typical application data.
What is the purpose of the VFF pin on the UCC38500N?
The VFF pin on the UCC38500N outputs a voltage proportional to the RMS value of the AC input line - generated by mirroring the IAC current into an external RC filter. At low line (85 VRMS), VFF ≈ 1.4 V; at high line (265 VRMS), VFF ≈ 4.7 V. This feedforward signal enables constant input power regulation across a 3:1 input voltage range without high-voltage sensing components.
Can the UCC38500N be used with a flyback converter as the second stage?
No - the UCC38500N is not recommended for flyback topologies. Its second-stage architecture assumes transformer-isolated, duty-cycle-limited operation (≤50%) with external error feedback on VERR and peak-current sensing on ISENSE2. Flyback lacks natural transformer reset control and violates the 50% duty-cycle constraint; TI explicitly recommends forward or half-bridge topologies for the second stage in SLUS419C.
What is the function of the OVP/ENBL pin on the UCC38500N?
The OVP/ENBL pin on the UCC38500N serves dual roles: as a window comparator, it disables the PFC gate driver (GT1) if the boost output exceeds +6.67% of nominal (overvoltage protection); and as an enable input, it disables both GT1 and GT2 and resets SS2 when pulled below 1.9 V - allowing system-level shutdown or brownout coordination.
UCC38500N Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-DIP (0.300", 7.62mm)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Mode:
- Average Current
- Frequency - Switching:
- 100kHz
- Current - Startup:
- 150 µA
- Voltage - Supply:
- 9.7V ~ 18V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 20-PDIP
UCC38500N FAQ
1.How can I place an order for UCC38500N through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC38500N on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC38500N reliable?
The price and inventory of UCC38500N are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC38500N is usually 5 days.
3.What payment methods are accepted for UCC38500N?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC38500N transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC38500N?
UCC38500N orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC38500N order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC38500N?
For technical support, including UCC38500N datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC38500N requirements.
6.How does Aetrix verify that UCC38500N is sourced from the original manufacturer or authorized distributors?
All UCC38500N products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC38500N meets industry standards.
7.What is the process for return or replacement of UCC38500N?
All UCC38500N units undergo pre-shipment inspection (PSI). If there is an issue with UCC38500N, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC38500N part is unused and in its original packaging.
Return procedure for UCC38500N:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UCC38500N Tags

-
ICE2PCS01GXUMA1
Infineon Technologies
-
NCP1654BD133R2G
onsemi
-
MC33262DR2G
onsemi

-
ICE3PCS03GXUMA1
Infineon Technologies
-
NCP1631DR2G
onsemi

-
L4981BD013TR
STMicroelectronics

-
UCC28070DWR
Texas Instruments

-
UCC28070PWR
Texas Instruments

-
UC3854DWTR
Texas Instruments

-
L4981AD013TR
STMicroelectronics
-
UCC2817D
Texas Instruments

-
UC2854BDWTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

