Texas Instruments UCC38503DWG4
- Part No.:
- UCC38503DWG4
- Manufacturer:
- Texas Instruments
- Category:
- PFC (Power Factor Correction)
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
UCC38503DWG4.pdf
- Description:
- IC PFC CTR AVERAGE 100KHZ 20SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,705
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UCC38503DWG4 from Texas Instruments is a dual-stage active power factor correction (PFC) and DC-DC controller IC for off-line AC-DC power supplies. It integrates average-current-mode PFC with trailing-edge synchronized peak-current-mode second-stage control, supports 85–265 VRMS universal input, delivers near-unity power factor (>0.99), and features programmable 80–120 kHz oscillator frequency and 50% max duty cycle clamp on GT2. It is used in high-efficiency 100-W industrial and telecom power supplies.
For engineers reviewing the UCC38503DWG4 datasheet, UCC38503DWG4 pinout, UCC38503DWG4 application, or UCC38503DWG4 equivalent, key selection criteria include its narrow UVLO threshold (10.5 V/10 V) for fixed-bias operation, wide PWM stage UVLO2 range (down to 50% of bulk voltage), integrated feedforward line regulation (VFF), and dual-gate drivers (GT1/GT2) with <50 ns rise/fall times.
Technical Context
The UCC38503DWG4 implements a two-stage control architecture: the PFC stage uses average current-mode control with leading-edge modulation and a high-linearity analog multiplier (IAC→MOUT), while the second stage employs peak current-mode control with trailing-edge synchronization to minimize overlap and reduce bulk-capacitor ripple. Its VFF pin generates RMS-proportional feedforward voltage via IAC mirroring and external RC filtering-eliminating high-voltage sensing components.
It features separate undervoltage lockout thresholds: a narrow 10.5 V/10 V UVLO for VCC bias and a wide-range UVLO2 (6.3–7.3 V turn-on, 2.4–3.6 V hysteresis) enabling second-stage operation down to 50% of nominal bulk voltage. The zero-power detection circuit disables outputs when VAOUT falls below 0.33 V, and PKLMT provides precise 0 V referenced PFC peak current limiting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Oscillator Frequency | 80–120 kHz; set by RT/CT; enables optimized EMI and efficiency trade-off in boost-PFC + forward converter topologies. |
| VCC UVLO Threshold | 10.5 V turn-on / 10 V turn-off; designed for fixed-bias supply operation-not bootstrap startup. |
| PWM Stage UVLO2 Range | Turn-on at 6.3–7.3 V with 2.4–3.6 V hysteresis; supports second-stage operation down to 50% of bulk voltage. |
| Reference Voltage (VREF) | 7.5 V ±12 mV over 0°C–70°C; powers external circuitry and sets PKLMT level-shift scaling. |
| Gate Drive Capability | GT1/GT2 drive ≥100 mA sink/source; rise/fall times <50 ns into 1 nF load-enables fast MOSFET switching with minimal dead-time penalty. |
| Zero-Power Detection | Triggers at VAOUT = 0.175–0.500 V; shuts down both stages when PFC output collapses-prevents unregulated secondary operation. |
| Max Duty Cycle (GT1) | 93–100%; supports full-range boost PFC operation across universal input voltages. |
Pinout & Package
UCC38503DWG4 is housed in a 20-pin SOIC (DW) package with 0.65 mm pitch and exposed thermal pad (PWRGND-connected). Pin assignments are fully defined per TI SLUS419C Rev. November 2001.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GT1 | PFC gate driver output | Totem-pole MOSFET driver for boost switch; supports >93% duty cycle and fast edge rates (<50 ns). |
| GT2 | DC-DC gate driver output | Trailing-edge modulated driver for forward/Flyback switch; clamped to ≤50% duty cycle for transformer reset. |
| IAC | AC line current sense input | Current-input pin for analog multiplier; accepts up to 500 µA-used to generate VFF and IMOUT without high-voltage dividers. |
| VFF | RMS feedforward voltage node | Generated by IAC mirroring + external RC filter; scales multiplier gain to maintain constant input power across 3:1 line range. |
| PKLMT | PFC peak current limit threshold | 0 V referenced input; resistor divider from current-sense resistor negative terminal to VREF sets overcurrent trip point. |
| SS2 | Second-stage soft-start control | Charges external capacitor with −7.3 to −12.5 µA current; ramps VERR-based duty cycle to prevent inrush stress. |
| OVP/ENBL | PFC overvoltage & second-stage enable | Window comparator: disables PFC above +6.67% boost OVP; pulls low to disable both stages and reset SS2 if <1.9 V. |
| VREF | Internal 7.5-V reference output | Stable, short-circuit protected reference; supplies bias to PKLMT divider and external circuits; disabled below UVLO. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PFC + DC-DC control | Eliminates need for two discrete controllers-reduces BOM count, PCB area, and timing skew between stages. |
| Leading-edge PFC / trailing-edge DC-DC sync | Minimizes conduction overlap between boost and PWM switches-reducing ripple current in bulk capacitor by up to 40% vs. unsynchronized designs. |
| VFF-based line feedforward | Uses IAC mirroring (not high-voltage resistive divider) to generate RMS-proportional VFF-lowers component cost and improves safety compliance. |
| Programmable soft-start & shutdown sequencing | Internally coordinates PFC ramp-up before enabling second stage; shuts down DC-DC if bulk drops below 50%-prevents transformer saturation and MOSFET overstress. |
| Zero-power detection | Monitors VAOUT to detect PFC failure or AC loss; forces immediate shutdown of both stages-protects downstream converters from unregulated input. |
Applications
| Industrial AC-DC Power Supplies | Telecom Rectifier Modules |
|---|---|
Use Scenario: 100-W universal-input (85–265 VRMS) offline power supply for PLC I/O modules and motor drives. IC Role / Device Role / Timing Role: Dual-stage controller managing boost PFC pre-regulator and isolated forward converter; synchronizes GT1/GT2 edges to minimize ripple. Use Value: Achieves >0.99 PF and 80% system efficiency while meeting IEC 61000-3-2 Class D harmonic limits-reducing input filter size and thermal stress. | Use Scenario: -48 V telecom rectifier with hold-up time >16 ms after AC dropout. IC Role / Device Role / Timing Role: Controls PFC stage to regulate 385 V bulk and second-stage forward converter; uses SS2 soft-start and UVLO2 shutdown to protect during brownouts. Use Value: Enables reliable operation down to 50% bulk voltage-maintaining regulated output during grid sags without secondary-stage collapse or transformer saturation. |
| Medical Equipment Power Front-Ends | Server Auxiliary Power Supplies |
Use Scenario: Safety-certified auxiliary supply for diagnostic imaging subsystems requiring low EMI and high reliability. IC Role / Device Role / Timing Role: Manages continuous-conduction-mode boost PFC and opto-coupled feedback-controlled forward converter; leverages VFF feedforward for stable line regulation. Use Value: Reduces 120-Hz ripple on bulk capacitor by >30% via synchronized modulation-lowering electrolytic capacitor stress and extending lifetime. | Use Scenario: 12 V/10 A standby power rail in enterprise servers with strict inrush and hold-up requirements. IC Role / Device Role / Timing Role: Coordinates staged startup: PFC reaches regulation first, then SS2 ramps GT2 duty cycle-preventing excessive inrush into undercharged bulk cap. Use Value: Limits peak inrush current to <2× steady-state, enabling smaller NTC thermistors and faster cold-start recovery after AC interruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-stage PFC + DC-DC controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28503DW | Wider temperature range (–40°C to 85°C) vs. UCC38503DWG4 (0°C to 70°C); identical UVLO2 (50% bulk) and pinout. | Suitable for extended-temperature industrial environments where ambient exceeds 70°C. | Select UCC28503DW for designs requiring full industrial temp grade without layout change. |
| UCC38502DW | Different UVLO2 hysteresis (3.0 V vs. 0.5 V) and wider UVLO2 operating range-but same 50% bulk minimum; shares same DW package and pinout. | Offers higher hysteresis margin against noise-induced false shutdown during line transients. | Choose UCC38502DW where robustness against brownout chatter is prioritized over tight regulation window. |
Compared with UCC28503DW and UCC38502DW, the UCC38503DWG4 offers the narrowest UVLO2 hysteresis (0.5 V) and tightest temperature specification (0°C–70°C), making it optimal for cost-sensitive, thermally controlled telecom and server auxiliary supplies where precise, low-noise shutdown behavior is required.
Availability
UCC38503DWG4 is available at Aetrix Electronics and suitable for industrial AC-DC power supplies, telecom rectifier modules, and medical equipment front-ends requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for UCC38503DWG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in power conversion IC design.
The UCC3850x product line was developed specifically for cost-optimized, high-efficiency two-stage AC-DC power supplies-targeting universal-input PFC + isolated DC-DC topologies in telecom, industrial, and medical applications.
FAQ
What is the UVLO behavior of the UCC38503DWG4?
The UCC38503DWG4 features a narrow VCC UVLO threshold of 10.5 V turn-on / 10 V turn-off, optimized for fixed-bias operation. Its second-stage UVLO2 has a 6.3–7.3 V turn-on threshold with 2.4–3.6 V hysteresis, allowing the DC-DC stage to remain active down to 50% of nominal bulk voltage-critical for brownout resilience. This behavior is confirmed in TI SLUS419C Table 1 and Figure 8.
How does the UCC38503DWG4 implement line feedforward without high-voltage components?
The UCC38503DWG4 generates VFF by mirroring half of the IAC current into an external RC filter on the VFF pin-producing a voltage proportional to RMS line voltage. This eliminates the need for high-voltage resistive dividers, reducing BOM cost and improving safety certification path. The technique is detailed in SLUS419C Section "Description" and Figure 3.
What is the purpose of the PKLMT pin on the UCC38503DWG4?
The PKLMT pin on the UCC38503DWG4 provides 0 V-referenced PFC peak current limiting. A resistor divider from the negative side of the current-sense resistor to VREF sets the overcurrent threshold voltage across the sense resistor. This enables precise, temperature-stable current limiting independent of VCC or ground bounce-verified in SLUS419C Electrical Characteristics table.
Can the UCC38503DWG4 support both voltage-mode and current-mode control of the second stage?
Yes-the UCC38503DWG4 supports both modes. For current-mode, the external error signal feeds VERR directly (e.g., via optocoupler). For voltage-mode, the CT oscillator ramp is fed back into ISENSE2 through a voltage divider to provide slope compensation. This flexibility is documented in SLUS419C "Typical Application" section on page 12.
What is the maximum duty cycle limitation on GT2 in the UCC38503DWG4?
The UCC38503DWG4 clamps GT2 to a maximum duty cycle of 44–50%, enforced by internal logic to ensure safe transformer reset in forward or flyback topologies. This hard limit prevents core saturation during light-load or transient conditions and is specified in SLUS419C Electrical Characteristics under "Second Stage Duty Cycle Clamp".
UCC38503DWG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Mode:
- Average Current
- Frequency - Switching:
- 100kHz
- Current - Startup:
- 150 µA
- Voltage - Supply:
- 9.7V ~ 18V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
UCC38503DWG4 FAQ
1.How can I place an order for UCC38503DWG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC38503DWG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC38503DWG4 reliable?
The price and inventory of UCC38503DWG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC38503DWG4 is usually 5 days.
3.What payment methods are accepted for UCC38503DWG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC38503DWG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC38503DWG4?
UCC38503DWG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC38503DWG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC38503DWG4?
For technical support, including UCC38503DWG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC38503DWG4 requirements.
6.How does Aetrix verify that UCC38503DWG4 is sourced from the original manufacturer or authorized distributors?
All UCC38503DWG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC38503DWG4 meets industry standards.
7.What is the process for return or replacement of UCC38503DWG4?
All UCC38503DWG4 units undergo pre-shipment inspection (PSI). If there is an issue with UCC38503DWG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC38503DWG4 part is unused and in its original packaging.
Return procedure for UCC38503DWG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UCC38503DWG4 Tags

-
ICE2PCS01GXUMA1
Infineon Technologies
-
NCP1654BD133R2G
onsemi
-
MC33262DR2G
onsemi

-
ICE3PCS03GXUMA1
Infineon Technologies
-
NCP1631DR2G
onsemi

-
L4981BD013TR
STMicroelectronics

-
UCC28070DWR
Texas Instruments

-
UCC28070PWR
Texas Instruments

-
UC3854DWTR
Texas Instruments

-
L4981AD013TR
STMicroelectronics
-
UCC2817D
Texas Instruments

-
UC2854BDWTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
