Texas Instruments UCC3882PW
- Part No.:
- UCC3882PW
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
UCC3882PW.pdf
- Description:
- IC REG CTRLR INTEL 1OUT 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,998
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UCC3882PW from Texas Instruments is a 28-pin average current mode synchronous buck controller with integrated 5-bit DAC, designed for high-end microprocessor VRM applications. It delivers programmable output voltage (1.8–3.5 V in 50/100 mV steps), 1% DAC/reference combined accuracy, foldback current limiting, and dual totem-pole gate drivers supporting up to 700 kHz switching frequency - enabling precise regulation of Pentium® II-class CPU core supplies.
For engineers reviewing the UCC3882PW datasheet, UCC3882PW pinout, UCC3882PW application, or UCC3882PW equivalent, this device is critical for designing high-efficiency, tightly regulated synchronous buck converters where VID code compatibility, OVP/UVLO fault windows, and cross-conduction prevention are mandatory design requirements.
Technical Context
The UCC3882PW implements average current mode control using a dedicated current sense amplifier (16× gain) and current amplifier (CAO/CAM loop), with COMP output feeding a PWM comparator referenced to oscillator ramp. Its 5-bit DAC directly interprets Intel-compatible VID codes to generate the COMMAND voltage - the non-inverting input of the voltage error amplifier - establishing the target output regulation point.
Two independent overvoltage comparators monitor VSNS: one triggers PWRGD reset at ±9% deviation (UV/OV), while a second forces GATEHI off/GATELO on at +17.5% overvoltage. Gate drive timing includes programmable dead time via RT, and built-in foldback reduces short-circuit current limit to 50% when output drops below 50% of COMMAND voltage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DAC Output Range | 1.3 V–3.5 V in discrete 50 mV (1.3–2.05 V) or 100 mV (2.1–3.5 V) steps; sets exact CPU core voltage per VID code |
| DAC + Reference Accuracy | ±1% combined error ensures output voltage stays within ±1% of programmed COMMAND voltage across temperature |
| Oscillator Frequency | Programmable 300–420 kHz (typ. 360 kHz); set by RT/CT; supports up to 700 kHz with external tuning |
| Current Sense Gain | 16 V/V fixed gain enables use of low-value (e.g., 5 mΩ) sense resistors, minimizing conduction loss |
| Foldback Current Limit | Clamps short-circuit current to 50% nominal when output falls below 50% of COMMAND voltage, reducing MOSFET stress |
| UVLO Thresholds | Turn-on at 10.5–10.8 V, turn-off at 9.5–10.0 V; hysteresis ≥300 mV prevents supply chatter during brownout |
| GATEHI/GATELO Drive | 2 Ω totem-pole outputs; 11.8 V high / 0.2 V low at 100 mA; rise/fall <80 ns into 3.3 nF load |
Pinout & Package
Packaged in a 28-pin wide-body SOIC (PW), the UCC3882PW features separate power grounds (GND and PGND), dual gate driver supplies (VDRVHI/VDRVLO), and dedicated pins for VID inputs (D0–D4), current sensing (IS+/IS−), and system monitoring (VSNS, PWRGD).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5 | D0–D4 digital inputs | Set 5-bit VID code; internal pull-ups enable logic-high detection via floating or 5 V tie; define COMMAND voltage and enable/disable behavior |
| 6 | EN | Active-low chip disable; pulls GATEHI/GATELO low when grounded; internally pulled up to 5 V |
| 7, 8 | IS+, IS− | Differential inputs to current sense amplifier; measure voltage across low-side sense resistor for average current mode control |
| 9, 10 | VFB, COMP | VFB = inverting input of voltage error amp; COMP = output node; feedback network between them sets loop compensation and stability |
| 11, 12 | GATELO, PGND | GATELO drives low-side synchronous MOSFET; PGND is dedicated return path for gate drivers and VDRVLO bypass |
| 13, 14 | RT, CT | Set oscillator frequency and gate drive dead time; RT also programs delay between GATEHI turn-off and GATELO turn-on |
| 15, 16 | VIN, GND | VIN powers internal circuitry (10.8–15 V); GND is analog/digital reference for all non-power pins except gate drivers |
| 17, 18 | VDRVHI, GATEHI | VDRVHI supplies high-side driver; GATEHI drives high-side MOSFET with 2 Ω push-pull output and anti-cross-conduction timing |
| 19, 20 | VREF, VSNS | VREF = 5 V precision reference (current-limited); VSNS monitors output voltage for PWRGD, OVP, UV, and foldback functions |
| 21, 22 | PWRGD, CAM | PWRGD = open-drain reset signal (≤470 Ω on-resistance); CAM = inverting input of current amplifier for loop compensation |
| 23, 24 | CAO, ISOUT | CAO = current amplifier output (0.5–2.5 V range); ISOUT = amplified sense voltage (COMMAND + 16×Vsense) used for current limiting |
| 25, 26, 27, 28 | NC, NC, COMMAND, OSOUT | NC = no internal connection; COMMAND = DAC output / voltage error amp non-inverting input; OSOUT = oscillator output (not user-accessible) |
Key Features
| Feature | Design Value |
|---|---|
| Intel-compatible 5-bit VID DAC | Directly accepts standard Pentium® II VID codes (D0–D4) to set 1.3–3.5 V output in precise 50/100 mV increments |
| Programmable dead-time control | RT pin adjusts GATEHI-to-GATELO and GATELO-to-GATEHI transition delays to eliminate MOSFET cross-conduction |
| Dual overvoltage protection | Separate comparators trigger PWRGD reset at +9%/−9% and force safe shutdown at +17.5%, preventing CPU damage |
| Low-offset current sense amplifier | 1 mV max input offset enables accurate current measurement with sub-10 mΩ sense resistors, preserving efficiency |
| Foldback current limiting | Reduces short-circuit current limit to 50% of nominal when output collapses, lowering thermal stress on MOSFETs and capacitors |
| Integrated 5 V reference (VREF) | Stable, current-limited 5 V source powers DAC and UVLO comparator; requires 0.01 µF low-ESR bypass to GND |
Applications
| Desktop CPU Core Supply | Laptop VRM Module |
|---|---|
Use Scenario: Regulating core voltage for Pentium® II and compatible microprocessors requiring dynamic VID-based voltage scaling. IC Role / Device Role / Timing Role: Primary synchronous buck controller implementing average current mode control, DAC-based voltage setpoint, and real-time OVP/UVLO monitoring. Use Value: Enables compliance with Intel VRM 8.1 specifications including ±1% output accuracy, fast transient response, and 17 A short-circuit current handling. |
Use Scenario: Powering mobile CPU cores in space-constrained laptop platforms where thermal management and efficiency are critical. IC Role / Device Role / Timing Role: Dual-MOSFET gate driver and current-mode controller managing 5 V or 12 V input conversion to 1.8–2.8 V output with foldback protection. Use Value: Reduces heat generation via synchronous rectification and foldback current limiting, extending battery life and improving reliability under load transients. |
| Server VRM Reference Design | Industrial Embedded CPU Supply |
Use Scenario: Building scalable, high-current (15+ A) VRM solutions for multi-socket server motherboards with strict DC-DC regulation requirements. IC Role / Device Role / Timing Role: Central controller coordinating gate timing, current sensing, and fault signaling across parallel-phase designs using external synchronization. Use Value: Supports stable operation across 0°C–70°C ambient with 1% DAC accuracy and programmable oscillator frequency for EMI optimization. |
Use Scenario: Delivering tightly regulated CPU core power in ruggedized industrial controllers where long-term supply continuity and fault resilience matter. IC Role / Device Role / Timing Role: Fault-tolerant synchronous controller providing PWRGD reset, dual OVP thresholds, and undervoltage lockout for fail-safe boot sequencing. Use Value: Ensures deterministic power-up/down behavior and prevents brownout-induced CPU corruption via 300–700 mV UVLO hysteresis. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC3882PWP | Same die, TSSOP-28 package; identical electrical specs but smaller footprint and different thermal profile | Suitable for space-constrained PCBs where SOIC-28 height or solder joint reliability is a concern | Select UCC3882PWP only if board layout allows TSSOP-28 and thermal derating is verified |
| TPS51116PWR | Single-chip VRM solution with integrated MOSFET drivers and 3.3 V LDO; lacks 5-bit DAC but supports SMBus interface and enhanced telemetry | Targets newer Intel mobile platforms requiring SMBus communication and multi-rail support | Choose TPS51116PWR for SMBus-enabled systems; UCC3882PW remains optimal for legacy VID-only designs |
Compared with UCC3882PWP, the UCC3882PW offers superior thermal dissipation in SOIC-28 but requires more board area; versus TPS51116PWR, it provides simpler VID-only control without SMBus overhead but lacks integrated telemetry and multi-rail capability.
Availability
UCC3882PW is available at Aetrix Electronics and suitable for desktop CPU core supplies, laptop VRM modules, and industrial embedded CPU power systems requiring stable component supply, long-lifecycle support, and traceable sourcing.
Supply support for UCC3882PW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management ICs for computing and industrial applications.
The UCC3882PW belongs to TI's legacy Unitrode VRM controller family, engineered specifically for high-accuracy, high-current synchronous buck regulation in Intel Pentium® II–era CPU power delivery systems.
FAQ
What is the function of the COMMAND pin on the UCC3882PW?
The COMMAND pin on the UCC3882PW is the output of its integrated 5-bit DAC and serves as the non-inverting input to the voltage error amplifier. It sets the target output voltage based on D0–D4 VID code inputs - ranging from 1.3 V to 3.5 V in defined steps - and directly determines the regulated core voltage delivered to the CPU. The UCC3882PW uses this voltage as the reference for both voltage loop control and foldback current limiting.
How does the UCC3882PW implement overvoltage protection?
The UCC3882PW implements two-tier overvoltage protection: a primary ±9% window on VSNS triggers the open-drain PWRGD signal to reset the CPU, while a secondary +17.5% threshold digitally forces GATEHI off and GATELO on to achieve 0% duty cycle. Both comparators reference the COMMAND voltage, ensuring protection scales with the programmed output level. This dual mechanism prevents CPU damage during transient overvoltage events without relying on external circuitry.
Can the UCC3882PW operate from a 5 V input supply?
Yes, the UCC3882PW can operate from a 5 V input supply when configured appropriately: VIN must be ≥10.8 V, so a 5 V rail cannot power VIN directly. However, the device supports 5 V systems by connecting VIN to a boosted or auxiliary 12 V supply, while using 5 V for VDRVLO to drive logic-level low-side MOSFETs. The UCC3882PW datasheet confirms compatibility with both 5 V and 12 V input architectures through proper assignment of VDRVHI/VDRVLO and VIN rails.
What is the purpose of the foldback current limit in the UCC3882PW?
The foldback current limit in the UCC3882PW reduces the short-circuit current limit to 50% of its nominal value when the output voltage collapses below 50% of the COMMAND voltage. This feature minimizes power dissipation in external MOSFETs and output capacitors during sustained short-circuit conditions, enhancing system reliability and thermal safety. For example, with a 17 A nominal limit, foldback engages at ~8.5 A when VOUT drops near 0.9 V (for a 1.8 V COMMAND), protecting components without requiring external current-limit circuitry.
How is gate drive dead time controlled on the UCC3882PW?
Gate drive dead time on the UCC3882PW is controlled via the RT pin, which programs the delay between GATEHI turn-off and GATELO turn-on (150 ns typ.) and between GATELO turn-off and GATEHI turn-on (135 ns typ.). This internal timing eliminates cross-conduction in synchronous buck topologies by ensuring neither MOSFET is on simultaneously. The RT resistor value (10–50 kΩ recommended) sets both oscillator frequency and dead time, allowing designers to optimize efficiency and EMI performance with a single component.
UCC3882PW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VID code
- Voltage - Input:
- 5V, 12V
- Number of Outputs:
- 1
- Voltage - Output:
- 1.8V ~ 2.05V, 2.1V ~ 3.5V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP
UCC3882PW FAQ
1.How can I place an order for UCC3882PW through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC3882PW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC3882PW reliable?
The price and inventory of UCC3882PW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC3882PW is usually 5 days.
3.What payment methods are accepted for UCC3882PW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC3882PW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC3882PW?
UCC3882PW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC3882PW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC3882PW?
For technical support, including UCC3882PW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC3882PW requirements.
6.How does Aetrix verify that UCC3882PW is sourced from the original manufacturer or authorized distributors?
All UCC3882PW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC3882PW meets industry standards.
7.What is the process for return or replacement of UCC3882PW?
All UCC3882PW units undergo pre-shipment inspection (PSI). If there is an issue with UCC3882PW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC3882PW part is unused and in its original packaging.
Return procedure for UCC3882PW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UCC3882PW Tags

-
TPS51206DSQR
Texas Instruments

-
TPS51200DRCR
Texas Instruments

-
TPS51200DRCT
Texas Instruments

-
TPS62740DSSR
Texas Instruments

-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi

-
RT9026GSP
Richtek USA Inc.

-
LP2998MRX/NOPB
Texas Instruments

-
TPS51200QDRCRQ1
Texas Instruments

-
DPA423GN-TL
Power Integrations

-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

