Texas Instruments UCC3911DP-1
- Part No.:
- UCC3911DP-1
- Manufacturer:
- Texas Instruments
- Category:
- Battery Management
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
UCC3911DP-1.pdf
- Description:
- IC BATT PROT LI-ION 2CELL 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,892
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Product details
Overview
UCC3911DP-1 from Texas Instruments is a two-cell lithium-ion/lithium-polymer battery pack protector IC with integrated series FET switch, 4.20 V typical overvoltage threshold, 2.50 V undervoltage threshold, 3-A continuous current capacity, and 20 µA quiescent supply current - used in PDA and digital camera battery packs to prevent cell damage from overcharge/overdischarge.
For engineers reviewing the UCC3911DP-1 datasheet, UCC3911DP-1 pinout, UCC3911DP-1 application, or UCC3911DP-1 equivalent, this page delivers verified functional role, validated protection thresholds, confirmed SOIC-16 pin mapping, and real-world short-circuit delay behavior using CDLY capacitor tuning.
Technical Context
The UCC3911DP-1 implements a dual-threshold state machine with precision bandgap reference for independent per-cell voltage monitoring, enabling overvoltage (OV) and undervoltage (UV) detection with hysteresis via VOVR (3.70 V typ) and UUVR (3.00 V typ). Its internal charge pump drives the integrated FET to achieve low RDS(on), while sleep mode activation at UV reduces current draw to ~3 µA.
Short-circuit protection uses a user-configurable delay (100 µs nominal, extendable via CDLY–B0 capacitor) with 5.25 A typical trip threshold; chip enable (CE) allows assembly-safe FET disable with 4 µA standby current. Thermal shutdown activates at 165°C, and SUBS pins support isolated heat sinking for high-current operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Overvoltage Threshold | 4.20 V (typ), ±0.05 V tolerance - sets precise upper limit before disabling charge path to prevent Li-ion cell degradation |
| Undervoltage Threshold | 2.50 V (typ), ±0.08 V tolerance - triggers FET cutoff and sleep mode to avoid deep discharge-induced cell failure |
| Continuous Current Rating | 3 A - supports sustained load currents in portable electronics without external FETs |
| Quiescent Supply Current | 20 µA (normal), 3 µA (sleep) - minimizes self-discharge during storage and idle periods |
| Short-Circuit Delay | 100 µs (nominal), adjustable via CDLY capacitor - prevents nuisance tripping during capacitive load inrush |
| Operating Temperature | –20°C to 70°C - matches standard Li-ion battery thermal envelope for reliable field operation |
| Package | SOIC-16 (DP) - surface-mount footprint compatible with automated battery pack assembly |
Pinout & Package
UCC3911DP-1 is housed in a 16-pin SOIC (DP) package with exposed substrate pads (SUBS) for thermally isolated heat sinking. Pin 1 is NC; pins 6 and 7 are GND; pins 10 and 11 are B0; pins 4, 5, 12, and 13 are SUBS; and pin 9 is CE.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| B0 (pins 10,11) | Negative terminal connection of lower cell | Main current return path; referenced for all internal voltage measurements and FET source |
| B1 (pin 14) | Junction between lower-cell (+) and upper-cell (–) | Enables individual cell voltage monitoring for balanced two-cell stack protection |
| B2 (pin 16) | Positive terminal of upper cell / pack output (+) | High-side sense input; also supplies power to internal circuitry including charge pump |
| GND (pins 6,7) | Pack output (–) terminal | Bi-directional current path - conducts charge current into pack and discharge current out of pack |
| CDLY (pin 15) | Short-circuit delay timing control | Connects to B0 via capacitor to linearly extend trip delay up to milliseconds for surge-tolerant operation |
| CE (pin 9) | Chip enable input | Pull-low disables FET and reduces supply current to 4 µA - enables safe battery pack assembly and storage |
| OV (pin 2) | Active-low overvoltage status flag | Signals OV condition to host system; drives light loads only; used for charger interlock |
| UV (pin 3) | Active-low undervoltage status flag | Triggers sleep mode and disables discharge; indicates critical low-voltage state requiring recharge |
| LPWARN (pin 8) | Active-high low-power warning | Asserts at 3.0 V/cell to alert host before UV threshold - enables graceful system shutdown |
| SUBS (pins 4,5,12,13) | Isolated substrate connections | Must connect to electrically isolated heatsink - no grounding allowed - to manage FET thermal rise at 3 A |
Key Features
| Feature | Design Value |
|---|---|
| Integrated series FET switch | Eliminates need for external MOSFETs and associated gate-drive components - reduces BOM count and PCB area in compact battery packs |
| User-adjustable short-circuit delay | Capacitor on CDLY pin extends trip time beyond 100 µs - accommodates high-capacitance loads without false triggering |
| Cell-level voltage monitoring | Dual-sense architecture (B0/B1/B2) detects imbalance - prevents single-cell overvoltage/undervoltage even when total pack voltage appears nominal |
| Thermal shutdown protection | 165°C junction limit - safeguards against FET thermal runaway during sustained overload or poor heatsinking |
| Assembly-safe chip enable | CE pin held low during pack build disables FET and cuts supply current to 4 µA - prevents accidental activation before final link cut |
Applications
| PDA Battery Protection | Digital Camera Power Management |
|---|---|
Use Scenario: Portable digital assistant with removable two-cell Li-ion battery subject to frequent partial charging and variable load profiles. IC Role / Device Role / Timing Role: Primary cell-level protector enforcing per-cell voltage limits and blocking unsafe charge/discharge paths. Use Value: Prevents capacity loss and swelling by halting charge above 4.20 V/cell and discharge below 2.50 V/cell - extending usable cycle life beyond 300 cycles. |
Use Scenario: High-current burst discharge during flash charging and image capture in compact digital cameras. IC Role / Device Role / Timing Role: Bidirectional current controller with configurable short-circuit delay to tolerate flash capacitor inrush. Use Value: CDLY-tuned 500 µs delay avoids false trips during 2-A flash charge transients while still protecting against true shorts. |
| Camcorder Battery Safety | Private Mobile Radio Pack Monitoring |
Use Scenario: Extended video recording causing gradual cell imbalance and elevated temperature in sealed camcorder battery modules. IC Role / Device Role / Timing Role: Dual-threshold monitor with thermal shutdown and LPWARN early-alert signaling. Use Value: LPWARN asserts at 3.0 V/cell to trigger low-battery UI warnings 500 mV before UV cutoff - enabling graceful recording stop before data loss. |
Use Scenario: Mission-critical two-cell Li-ion packs in handheld radios exposed to wide ambient temperatures and intermittent high-power RF transmission. IC Role / Device Role / Timing Role: Robust protector operating across –20°C to 70°C with hysteresis to prevent oscillation near thresholds. Use Value: VOVR = 3.70 V and UUVR = 3.00 V provide 0.5 V hysteresis - eliminates chatter during voltage recovery after load removal. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar battery protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| BQ29700DR | Single-cell only; 4.25 V fixed OV threshold; no CDLY adjustment; 1.5 µA sleep current | Lacks two-cell sensing and adjustable short-circuit delay - unsuitable for stacked Li-ion packs requiring per-cell monitoring | Select only for single-cell designs where ultra-low quiescent current outweighs missing features |
| MP2617GJ-Z | Two-cell capable; integrates charge controller; 4.225 V OV; requires external FETs; 30 µA operating current | Combines protection + charging functions but increases component count and layout complexity | Choose when full battery management (charge + protect) is needed in same footprint - not a drop-in replacement |
Compared with UCC3911DP-1, BQ29700DR lacks multi-cell support and programmable fault timing, while MP2617GJ-Z adds charging functionality at the cost of higher system integration effort and reduced protection autonomy.
Availability
UCC3911DP-1 is available at Aetrix Electronics and suitable for PDA, digital camera, and camcorder battery pack designs requiring stable component supply, long-lifecycle assurance, and consistent SOIC-16 packaging for automated assembly.
Supply support for UCC3911DP-1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in battery safety ICs.
The UCC3911DP-1 belongs to TI's dedicated battery protection product line, engineered specifically for two-cell Li-ion/Li-Pol packs in portable consumer electronics - prioritizing reliability, low quiescent current, and integrated FET simplicity.
FAQ
What is the exact overvoltage threshold specification for UCC3911DP-1?
The UCC3911DP-1 has a guaranteed overvoltage threshold range of 4.15 V (min) to 4.25 V (max), with 4.20 V typical - measured per cell under –20°C to 70°C ambient conditions. This threshold is factory-trimmed and applies to both cells independently, ensuring precise protection without external calibration. The UCC3911DP-1 uses an internal bandgap reference for stability across temperature and supply variations.
How does UCC3911DP-1 handle cell imbalance during overvoltage or undervoltage events?
The UCC3911DP-1 monitors each cell individually via B0, B1, and B2 inputs - detecting overvoltage if either cell exceeds 4.20 V or undervoltage if either falls below 2.50 V. When imbalance occurs (e.g., one cell overcharged, the other undercharged), the device disables both charge and discharge paths simultaneously. This prevents further stress and signals failure via concurrent OV and UV assertion - a condition requiring pack replacement. The UCC3911DP-1 does not attempt cell balancing.
Can UCC3911DP-1 be used without the CDLY capacitor?
Yes, UCC3911DP-1 operates with CDLY open-circuit, delivering a fixed 100 µs short-circuit trip delay - sufficient for most resistive or moderate-capacitive loads. However, omitting the CDLY capacitor eliminates transient tolerance: high peak currents (e.g., flash charging) may cause nuisance trips. For robustness, TI recommends a 330 pF capacitor between CDLY and B0 - extending delay to ~600 µs at 7.2 V, as validated in the UCC3911DP-1 application circuit.
What is the function of the SUBS pins on UCC3911DP-1, and how must they be connected?
The four SUBS pins (4, 5, 12, 13) on UCC3911DP-1 connect internally to the silicon substrate and must be soldered to an electrically isolated copper pad or heatsink - never to system ground or any other signal. This isolation prevents latch-up and enables thermal dissipation during 3-A conduction. TI specifies that improper grounding of SUBS pins risks device failure; the UCC3911DP-1 relies on this isolated thermal path to maintain junction temperature below 150°C under worst-case load.
Does UCC3911DP-1 support battery pack assembly with zero power consumption before activation?
Yes - asserting CE low (connecting to B0) places UCC3911DP-1 in assembly mode, reducing supply current to ~4 µA while holding the internal FET off. This enables safe battery pack construction and long-term storage without self-discharge risk. Final activation occurs when the CE–B0 link is severed, allowing the internal 2-µA pull-up to enable normal operation. This feature is integral to UCC3911DP-1's design for high-reliability portable battery manufacturing.
UCC3911DP-1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Battery Protection
- Battery Chemistry:
- Lithium Ion/Polymer
- Number of Cells:
- 2
- Fault Protection:
- Over/Under Voltage, Short Circuit
- Interface:
- -
- Operating Temperature:
- -20°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
UCC3911DP-1 FAQ
1.How can I place an order for UCC3911DP-1 through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC3911DP-1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC3911DP-1 reliable?
The price and inventory of UCC3911DP-1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC3911DP-1 is usually 5 days.
3.What payment methods are accepted for UCC3911DP-1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC3911DP-1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC3911DP-1?
UCC3911DP-1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC3911DP-1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC3911DP-1?
For technical support, including UCC3911DP-1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC3911DP-1 requirements.
6.How does Aetrix verify that UCC3911DP-1 is sourced from the original manufacturer or authorized distributors?
All UCC3911DP-1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC3911DP-1 meets industry standards.
7.What is the process for return or replacement of UCC3911DP-1?
All UCC3911DP-1 units undergo pre-shipment inspection (PSI). If there is an issue with UCC3911DP-1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC3911DP-1 part is unused and in its original packaging.
Return procedure for UCC3911DP-1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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