Texas Instruments UCC5673MWP
- Part No.:
- UCC5673MWP
- Manufacturer:
- Texas Instruments
- Category:
- Signal Terminators
- Package:
- 36-BSOP (0.295", 7.50mm Width)
- Datasheet:
-
UCC5673MWP.pdf
- Description:
- IC SCSI 9-LINE TERM 36-SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UCC5673MWP from Texas Instruments is a multimode SCSI active terminator supporting both single-ended (SE) and low-voltage differential (LVD) termination for 9-line SCSI buses, operating from 2.7V to 5.25V TRMPWR, featuring auto-mode selection via DIFSENS/ DIFFB inputs, 105Ω differential impedance, and 3pF output capacitance per line.
For engineers reviewing the UCC5673MWP datasheet, UCC5673MWP pinout, UCC5673MWP application, or UCC5673MWP equivalent, this device serves as a critical bus-termination solution in legacy SCSI storage subsystems requiring mode-aware, low-capacitance, thermally robust termination with automatic SE/LVD/HVD detection and failsafe biasing.
Technical Context
The UCC5673MWP integrates dual termination networks-SE with ground-switched L+ lines and L– current-sinking loads, and LVD with matched 105Ω differential pairs biased at 125mV common-mode voltage-controlled by a 50Hz-filtered DIFFB comparator that interprets DIFSENS voltage levels (0.5V/0.7V/2.4V thresholds) to select SE, LVD, or high-impedance disconnect mode.
It includes dedicated regulators: a 1.25V LVD reference (±100mV tolerance) sourcing up to –420mA and sinking up to 420mA, and a 2.7V SE reference (±0.2V tolerance) with identical current capability; both support stable operation down to 2.7V TRMPWR, enabling compatibility with 3.3V ±10% systems including cable-drop margin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Range | 2.7V to 5.25V TRMPWR - supports 3.3V systems with full tolerance, fuse/diode drop, and cable loss margin |
| Differential Impedance | 100–110Ω - meets Ultra2/Ultra3 SCSI-3 differential bus impedance requirements for signal integrity |
| Output Capacitance | 3pF per line - satisfies SPI-2 specification limit of 10pF max per signal-to-ground in external terminators |
| Mode Change Delay | 100–300ms - ensures noise-immune, glitch-free transitions between SE/LVD/HVD modes after power-up or bus reconfiguration |
| Common-Mode Bias | 1.15–1.35V - provides stable 1.25V reference for LVD receivers across temperature and supply variation |
| Termination Current | –23mA typical (SE, 0.5V level) - delivers precise current-sink termination matching SCSI-2/SP-2 SE load requirements |
| Regulator Sink/Source | ±420mA - enables driving multiple parallel terminators or external bias networks without external buffering |
Pinout & Package
The UCC5673MWP is housed in a 36-pin MWP (QSOP-36) package with exposed thermal paddle, featuring two HS/GND pins for enhanced heat dissipation and optimized layout for SCSI bus routing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| L1+ to L9+ | SE ground switch / LVD positive termination | In SE mode: actively pulled to GND; in LVD mode: driven as positive differential pair terminal |
| L1– to L9– | SE current sink / LVD negative termination | In SE mode: sinks termination current; in LVD mode: driven as negative differential pair terminal |
| DIFSENS | SCSI bus mode sense input | Driven to 1.3V at power-up; shorted to GND by SE devices, pulled high by HVD devices, enabling automatic mode detection |
| DIFFB | Filtered mode selection comparator input | Accepts filtered DIFSENS voltage; thresholds at 0.5V (SE), 0.7–1.9V (LVD), >2.4V (HVD disconnect) |
| DISCNCT | Terminator enable/disable control | Open = active termination; grounded = high-impedance shutdown, used when not at bus end |
| TRMPWR | Main power input | Supplies all internal regulators and termination circuits; accepts 2.7–5.25V with 35mA (LVD) or 25mA (SE) typical supply current |
| HS/GND (2 pins) | Thermal ground connection | Directly bonded to die paddle; must connect to large PCB copper area or multi-layer ground plane to manage 130mW SE-mode dissipation |
Key Features
| Feature | Design Value |
|---|---|
| Auto-select multimode termination | Eliminates manual jumpering or firmware configuration by detecting bus mode via DIFSENS voltage level and applying correct SE or LVD network |
| Differential failsafe bias | Maintains 125mV differential bias and 1.25V common-mode voltage even under mismatched loading, ensuring receiver compatibility during hot-plug or partial bus activity |
| Built-in SPI-3 mode change filter/delay | 100–300ms hardware debounce prevents false mode switching due to transient noise on DIFFB, guaranteeing stable operation during bus arbitration |
| Reversed disconnect polarity | DISCNCT pin uses open-circuit = active, grounded = disabled - simplifies mechanical switch integration and avoids accidental disable via floating traces |
| Low 3pF channel capacitance | Meets Ultra2/Ultra3 SCSI-3 interconnect specs for external terminators, minimizing signal distortion and timing skew on high-speed parallel buses |
Applications
| SCSI Host Adapter Termination | External Cable Terminator Module |
|---|---|
Use Scenario: Integrated into a PCI-based SCSI host adapter PCB to terminate the internal bus end where SE and LVD peripherals coexist. IC Role / Device Role / Timing Role: Active multimode terminator providing real-time SE/LVD mode selection and regulated biasing for 9 control lines. Use Value: Enables backward-compatible operation with legacy SE drives while supporting newer LVD tape libraries, eliminating need for manual mode switches or dual-terminator designs. | Use Scenario: Mounted in an external SCSI-3 compliant terminator box connected to the far end of a wide SCSI cable run. IC Role / Device Role / Timing Role: Low-capacitance, thermally managed termination node delivering precise 105Ω differential impedance and 3pF loading per line. Use Value: Meets SPI-2 capacitance limits (10pF max per line to ground) and balance requirements (0.75pF intra-pair), preserving signal integrity at Ultra160 speeds. |
| RAID Controller Backplane Termination | SCSI Tape Library Interface Board |
Use Scenario: Embedded on a backplane board connecting multiple hot-swappable SCSI disk drives with mixed SE/LVD signaling. IC Role / Device Role / Timing Role: Mode-detecting terminator managing termination state across all 27 SCSI lines (9 control + 18 data) via three UCC5673MWP units sharing one DIFSENS line. Use Value: Ensures reliable bus initialization and dynamic reconfiguration during drive insertion/removal without software intervention or bus reset. | Use Scenario: Installed on a tape library's front-end interface card to terminate the SCSI bus between robotic controller and tape drives. IC Role / Device Role / Timing Role: High-reliability termination IC with 150°C junction rating and HS/GND thermal pads, operating continuously in enclosed, airflow-limited enclosures. Use Value: Sustains 130mW per active line in SE mode at 5.25V TRMPWR without derating, supported by direct die-to-PCB thermal conduction via HS/GND pins. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SCSI multimode termination applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC5673PW | 28-pin TSSOP package; lacks HS/GND thermal pins; 35mA LVD supply current vs. 35mA (same); identical electrical specs | Lower thermal capacity; unsuitable for sustained SE-mode operation in high-density enclosures without supplemental cooling | Select UCC5673PW only for space-constrained, low-power SE-only or intermittent-use applications where thermal management is externally assured. |
| MAX3243CPE+ | RS-232 transceiver with integrated charge pump; no SCSI termination logic, no DIFSENS/DIFFB interface, no multimode capability | Not functionally comparable - designed for serial communication, not parallel SCSI bus termination | Not a valid alternative; MAX3243CPE+ serves entirely different interface standards and cannot replace UCC5673MWP in SCSI termination roles. |
Compared with UCC5673PW, the UCC5673MWP offers superior thermal performance via dedicated HS/GND pins and QSOP-36 layout, making it the only suitable choice for continuous-duty SCSI backplanes; MAX3243CPE+ is incompatible due to fundamental functional mismatch.
Availability
UCC5673MWP is available at Aetrix Electronics and suitable for SCSI host adapters, external cable terminators, RAID backplanes, and tape library interface boards requiring stable component supply across long-lifecycle industrial storage programs.
Supply support for UCC5673MWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.
The UCC5673MWP belongs to TI's legacy SCSI interface product line, engineered specifically for robust, auto-configuring parallel bus termination in mixed-mode storage subsystems where SE, LVD, and HVD devices coexist on the same SCSI chain.
FAQ
What is the primary function of the UCC5673MWP in a SCSI system?
The UCC5673MWP serves as an auto-selecting multimode active terminator for 9-line SCSI buses, dynamically configuring itself for single-ended (SE) or low-voltage differential (LVD) termination based on the DIFSENS bus signal. It ensures proper impedance matching, biasing, and failsafe operation across mixed-device SCSI environments, eliminating manual mode selection. The UCC5673MWP achieves this using internal regulators, precision comparators, and thermally optimized packaging to maintain signal integrity at Ultra160 speeds.
How does the UCC5673MWP detect and switch between SE and LVD modes?
The UCC5673MWP monitors the DIFSENS line through its DIFFB input, which feeds a 50Hz noise-filtered comparator with defined thresholds: below 0.5V triggers SE mode, 0.7–1.9V selects LVD mode, and above 2.4V forces high-impedance disconnect for HVD buses. At power-up, the UCC5673MWP drives DIFSENS to 1.3V; presence of SE devices pulls it low, while LVD devices allow it to settle near 1.3V. This hardware-based detection requires no external microcontroller or configuration, and the UCC5673MWP applies the correct termination network within 300ms.
What thermal design considerations apply to the UCC5673MWP in SE-mode operation?
In SE mode, the UCC5673MWP can dissipate up to 130mW per active line at 5.25V TRMPWR, demanding careful thermal management. Its MWP package includes two dedicated HS/GND pins directly connected to the die paddle; these must be soldered to large PCB copper areas or multi-layer ground planes using at least four vias per pin. Unlike the TSSOP variant, the UCC5673MWP's thermal design supports continuous SE-mode operation in enclosed RAID or tape library enclosures without forced airflow, making it uniquely suited for high-reliability storage applications.
Does the UCC5673MWP meet Ultra3/Ultra160 SCSI timing and capacitance requirements?
Yes, the UCC5673MWP meets Ultra3/Ultra160 requirements for external terminators: its 3pF output capacitance per line complies with the SPI-2 10pF maximum per signal-to-ground limit, and its 0.1pF intra-pair and 0.3pF inter-pair capacitance balance exceeds the stringent 0.75pF and 2pF SPI-2 specifications. Combined with 105Ω differential impedance and 125mV differential bias, the UCC5673MWP preserves signal eye diagrams and timing margins at 160MB/s transfer rates, as validated in TI's application note UDG-99163.
Can the UCC5673MWP be used without external passive components?
No - the UCC5673MWP requires external support components for stable operation: a 0.1µF decoupling capacitor on DIFFB, a 20kΩ resistor between DIFFB and DIFSENS, and 4.7µF bulk capacitors on each TRMPWR pin. These components implement the mode-change filter, ensure noise immunity, and stabilize regulator outputs. The UCC5673MWP datasheet Figure 1 specifies exact placement and values; omitting them risks false mode switching, regulator instability, or failure to meet SCSI-3 compliance. All required external parts are documented for the UCC5673MWP in SLUS438.
UCC5673MWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 36-BSOP (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- SCSI, LVD, SE
- Number of Terminations:
- 9
- Voltage - Supply:
- 2.7V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-SSOP
UCC5673MWP FAQ
1.How can I place an order for UCC5673MWP through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC5673MWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC5673MWP reliable?
The price and inventory of UCC5673MWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC5673MWP is usually 5 days.
3.What payment methods are accepted for UCC5673MWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC5673MWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC5673MWP?
UCC5673MWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC5673MWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC5673MWP?
For technical support, including UCC5673MWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC5673MWP requirements.
6.How does Aetrix verify that UCC5673MWP is sourced from the original manufacturer or authorized distributors?
All UCC5673MWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC5673MWP meets industry standards.
7.What is the process for return or replacement of UCC5673MWP?
All UCC5673MWP units undergo pre-shipment inspection (PSI). If there is an issue with UCC5673MWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC5673MWP part is unused and in its original packaging.
Return procedure for UCC5673MWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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