My Inquiry
My Account
Texas Instruments UCD90120ARGCR
- Part No.:
- UCD90120ARGCR
- Manufacturer:
- Texas Instruments
- Category:
- Supervisors
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
UCD90120ARGCR.pdf
- Description:
- IC SUPERVISOR 12 CHANNEL 64VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:11,412
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UCD90120ARGCR from Texas Instruments is a 12-rail PMBus/I²C-addressable power-supply sequencer and monitor with closed-loop margining for up to 10 rails, 12-bit ADC (2.5 V ±0.5% internal reference), 400 μs per-rail sampling, and support for ACPI-compliant pin-selected rail states. It serves as the central system health controller in multi-rail server and telecom power systems.
For engineers reviewing the UCD90120ARGCR datasheet, UCD90120ARGCR pinout, UCD90120ARGCR application, or UCD90120ARGCR equivalent, key selection considerations include rail count (12), margining capability (10 rails), PMBus v1.1 compliance, GPIO flexibility (26 pins, 12 PWM-capable), and thermal performance (RθJA = 26.4°C/W).
Technical Context
The UCD90120ARGCR integrates a 12-bit SAR ADC with simultaneous sampling across 13 analog monitor inputs (MON1–MON13), supporting voltage monitoring from 0 V to 2.5 V (MON1–MON9) or 0.2 V to 2.5 V (MON10–MON13). Its sequencing engine uses time-based, rail-dependent, and pin-triggered logic with configurable on/off delays and fault-shutdown dependencies.
It implements closed-loop margining via eight FPWM outputs (15.26 kHz–125 MHz) and four GPI-configurable PWM outputs (0.93 Hz–7.81 MHz), enabling precise DC-DC output trimming. The device supports dual control domains: PMBus slave interface (10–400 kHz) and Boolean logic-driven GPIO control (up to 8 GPI inputs driving 12 programmable GPOs).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Rail Count | 12 independent voltage rails monitored and sequenced - enables full power management for complex SoC/FPGA systems. |
| ADC Resolution & Speed | 12-bit, 200 kSPS effective rate with 400 μs per-rail sampling - ensures real-time health visibility without aliasing in fast transient events. |
| Internal Reference | 2.5 V ±0.5% over 0°C–125°C - provides stable scaling for accurate rail margining and fault threshold detection. |
| Margining Capability | Closed-loop margining on up to 10 rails using FPWM/PWM outputs - allows automated four-corner testing and active DC-DC trim without external DACs. |
| PMBus Compliance | PMBus v1.1 slave with I²C/SMBus compatibility (10–400 kHz) - enables seamless integration into TI Fusion GUI and industry-standard power management ecosystems. |
| GPIO Resources | 26 GPIO pins: 12 with FPWM capability, 8 configurable as GPI, 12 as Boolean logic GPO - supports custom state machines, cascading, and hardware-triggered sequencing. |
| Package | VQFN-64 (9.0 mm × 9.0 mm, 0.5 mm pitch) with exposed thermal pad - optimized for high-density PCB layouts and thermal dissipation in industrial/telecom environments. |
Pinout & Package
VQFN-64 package (9.0 mm × 9.0 mm, 0.5 mm pitch) with exposed thermal pad connected to ground plane for thermal management. Pin functions validated per TI SLVSAN9C datasheet Rev. C (March 2019).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MON1–MON9 | Analog monitor input | 0–2.5 V rail sensing with 8 MΩ input impedance - directly interfaces with resistor-divider outputs of DC-DC converters. |
| MON10–MON13 | Analog monitor input | 0.2–2.5 V range, 0.5–1.5 MΩ impedance - supports low-voltage rails (e.g., 0.8 V, 1.2 V) with reduced divider loading. |
| FPWM1–FPWM8 | Configurable PWM output | 15.26 kHz–125 MHz frequency range - drives external margining DACs or PWM-controlled LDOs for precision closed-loop adjustment. |
| PMBUS_CLK / PMBUS_DATA | PMBus interface | Open-drain, 3.3 V pull-up required - enables bidirectional communication with host controllers for configuration and telemetry. |
| GPIO1–GPIO18, etc. | Programmable I/O | Supports GPI, GPO, PWM, JTAG, or system reset - enables hardware-triggered sequencing, fault propagation, and cascading across multiple UCD90120A devices. |
Key Features
| Feature | Design Value |
|---|---|
| 12-rail sequencing with dependency logic | Enables robust power-on/off order enforcement across heterogeneous rails (e.g., core, I/O, memory) while supporting fault-triggered shutdown chains. |
| Closed-loop margining (10 rails) | Automates production-level four-corner testing by dynamically adjusting rail voltages to user-defined UV/OV thresholds without host intervention. |
| Nonvolatile fault logging | Stores up to 12 timestamped fault entries (including peak values) in on-chip flash - accelerates field failure root-cause analysis without external memory. |
| Pin-selected rail states (ACPI) | Uses ≤3 GPIs to define 8 discrete rail configurations - implements low-power S0–S5 states compliant with Advanced Configuration and Power Interface standards. |
| Boolean logic GPO builder | Configures 12 GPOs using combinational logic of GPIs, POWER_GOOD, faults, and warnings - replaces discrete logic ICs for custom power-state arbitration. |
Applications
| Server Power Management | Telecom Line Card Sequencing |
|---|---|
|
Use Scenario: Sequencing and monitoring 12+ voltage rails (12 V, 5 V, 3.3 V, 1.8 V, 0.8 V) for CPU, memory, FPGA, and PHY on a dual-socket server motherboard. IC Role / Device Role / Timing Role: Central sequencer and health monitor coordinating turn-on timing, power-good assertion, and fault response across all rails. Use Value: Prevents latch-up and damage during boot by enforcing strict voltage ramp order; logs undervoltage events during thermal throttling for diagnostics. |
Use Scenario: Managing power sequencing for a 48 V backplane-fed line card with isolated DC-DCs supplying DSP, SerDes, and analog front-end circuits. IC Role / Device Role / Timing Role: PMBus-managed sequencer ensuring safe enable/disable order and real-time current/voltage monitoring per rail. Use Value: Enables hot-swap compliance and graceful shutdown during brownout; uses GPIO-cascading to synchronize multiple cards in a chassis. |
| Industrial ATE Power Control | FPGA-Based Test Equipment |
|
Use Scenario: Controlling 12 independently adjustable rails in automated test equipment requiring precise voltage margining for DUT power supply validation. IC Role / Device Role / Timing Role: Closed-loop margining controller performing four-corner testing (min/max VOUT) on each rail under software command. Use Value: Eliminates need for external margining DACs and reduces test setup complexity; stores pass/fail results with timestamps in nonvolatile memory. |
Use Scenario: Power sequencing for Xilinx UltraScale+ FPGA with >10 supply domains (VCCINT, VCCAUX, VCCO, GTY, etc.) and thermal sensors. IC Role / Device Role / Timing Role: System health manager monitoring rail voltages, temperatures (via TEMP0.8V/TEMP12V), and generating SYSTEM RESET on fault. Use Value: Detects early-stage rail drift before FPGA configuration failure; triggers WARN_OC_0.8V_OR_12V to alert host before catastrophic shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power-supply sequencing and monitoring applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCD90124ARGCT | 12-rail sequencer with identical pinout and feature set but includes integrated 12-bit ADC temperature sensor and enhanced fault logging (16 entries vs. 12). | Preferred where board space permits slightly larger VQFN-64 package and extended thermal telemetry is required. | Select UCD90124ARGCT when internal die temperature monitoring and deeper fault history are needed; otherwise UCD90120ARGCR offers cost-optimized feature parity. |
| UCD9090ARGCT | 10-rail sequencer with same architecture but reduced rail count, no FPWM margining outputs, and only 8 GPIOs (vs. 26). | Suitable for simpler systems with ≤10 rails and no closed-loop margining requirement. | Choose UCD9090ARGCT only if rail count and margining capability are not needed - UCD90120ARGCR provides full scalability without redesign. |
Compared with UCD90124ARGCT, UCD90120ARGCR trades integrated temperature sensing for lower BOM cost and identical sequencing/margining functionality; versus UCD9090ARGCT, it delivers 2 additional rails, 18 more GPIOs, and full closed-loop margining - making it the only option for complex, margining-intensive designs.
Availability
UCD90120ARGCR is available at Aetrix Electronics and suitable for server motherboard design, telecom line card development, industrial ATE systems, and FPGA-based test equipment requiring stable component supply and long-term lifecycle support.
Supply support for UCD90120ARGCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management ICs and digital power solutions.
The UCD90120ARGCR belongs to TI's Fusion Digital Power sequencer family, designed specifically for high-reliability, multi-rail power system control in servers, networking gear, and industrial equipment requiring PMBus-based telemetry and hardware-triggered sequencing.
FAQ
What is the maximum number of voltage rails the UCD90120ARGCR can monitor and sequence?
The UCD90120ARGCR monitors and sequences up to 12 independent voltage rails. Its 13 analog monitor inputs (MON1–MON13) allow oversampling or redundancy - for example, MON10–MON13 support low-voltage rails (0.2–2.5 V range) while MON1–MON9 cover standard 0–2.5 V ranges. All 12 rails are fully configurable for timing, dependencies, and fault responses in the TI Fusion GUI.
Does the UCD90120ARGCR support closed-loop margining, and how many rails can be margined?
Yes, the UCD90120ARGCR supports closed-loop margining on up to 10 voltage rails using its FPWM1–FPWM8 outputs and four additional PWM-capable GPIOs. Margining adjusts rail output voltages to match user-defined thresholds (e.g., ±3% UV/OV) in real time, enabling automated four-corner testing and active DC-DC trimming without external controllers.
What package type and thermal characteristics does the UCD90120ARGCR use?
The UCD90120ARGCR is housed in a 64-pin VQFN package (9.0 mm × 9.0 mm, 0.5 mm pitch) with an exposed thermal pad. Its thermal resistance is RθJA = 26.4°C/W (junction-to-ambient) and RθJB = 1.7°C/W (junction-to-board), confirming suitability for high-power-density applications when the thermal pad is soldered to a solid ground plane.
Can the UCD90120ARGCR operate without a PMBus host, using only GPIO control?
Yes, the UCD90120ARGCR supports fully autonomous operation via GPIO. Up to 8 GPI pins can drive Boolean logic to control 12 GPOs, enabling pin-selected rail states (e.g., ACPI S0–S5), hardware-triggered sequencing, and fault propagation - all without PMBus communication. This mode is ideal for systems lacking a PMBus master or requiring fail-safe local control.
How does the UCD90120ARGCR handle fault logging and system recovery?
The UCD90120ARGCR stores up to 12 timestamped fault entries (including peak voltage/current values) in on-chip nonvolatile flash memory. Fault responses - such as immediate shutdown, delayed sequencing off, or cascaded rail restart - are user-configurable via TI Fusion GUI. Recovery actions execute autonomously, with no host intervention required for basic fault containment.
UCD90120ARGCR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 12
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain, Push-Pull
- Reset:
- Active High/Active Low
- Reset Timeout:
- 2µs Minimum
- Operating Temperature:
- -40°C ~ 110°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (9x9)
UCD90120ARGCR FAQ
1.How can I place an order for UCD90120ARGCR through Aetrix?
Please submit a Request for Quotation (RFQ) for UCD90120ARGCR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCD90120ARGCR reliable?
The price and inventory of UCD90120ARGCR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCD90120ARGCR is usually 5 days.
3.What payment methods are accepted for UCD90120ARGCR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCD90120ARGCR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCD90120ARGCR?
UCD90120ARGCR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCD90120ARGCR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCD90120ARGCR?
For technical support, including UCD90120ARGCR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCD90120ARGCR requirements.
6.How does Aetrix verify that UCD90120ARGCR is sourced from the original manufacturer or authorized distributors?
All UCD90120ARGCR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCD90120ARGCR meets industry standards.
7.What is the process for return or replacement of UCD90120ARGCR?
All UCD90120ARGCR units undergo pre-shipment inspection (PSI). If there is an issue with UCD90120ARGCR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCD90120ARGCR part is unused and in its original packaging.
Return procedure for UCD90120ARGCR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UCD90120ARGCR Tags
-
MIC826SYMT-TR
Microchip Technology
-
APX803S-31SA-7
Diodes Incorporated
-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments
-
V6340RSP3B+
EM Microelectronic
-
EM6325CXSP5B-2.9+
EM Microelectronic
-
MCP120T-300I/TT
Microchip Technology
-
MCP130T-315I/TT
Microchip Technology
-
MCP120T-475I/TT
Microchip Technology
-
MCP111T-300E/TT
Microchip Technology
-
MCP120T-315I/TT
Microchip Technology
-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
