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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Texas Instruments UCD9080RHBRG4

Name: UCD9080RHBRG4
Brand: Texas Instruments
SKU: UCD9080RHBRG4
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: UCD9080RHBRG4

Manufacturer:: Texas Instruments

Category:: Supervisors

Package:: 32-VFQFN Exposed Pad

Datasheet:: UCD9080RHBRG4.pdf

Description:: IC SUPERVISOR 8 CHANNEL 32VQFN

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Product details

Overview

UCD9080RHBRG4 from Texas Instruments is an 8-channel digital power-supply sequencer and monitor IC operating from a single 3.3-V supply. It sequences up to eight voltage rails with 3.2-mV analog resolution, monitors rail voltages every 50 µs, and provides four configurable digital outputs for reset or status signaling - deployed in telecom switches, servers, and networking equipment.

For engineers reviewing the UCD9080RHBRG4 datasheet, UCD9080RHBRG4 pinout, UCD9080RHBRG4 application, or UCD9080RHBRG4 equivalent, key selection criteria include per-rail UV/OV threshold programmability, parent-rail–triggered sequencing logic, I²C slave interface timing compliance (10–100 kHz), and RHB QFN-32 package compatibility with high-density PCB layouts.

Technical Context

The UCD9080RHBRG4 integrates a 10-bit SAR ADC, I²C slave engine, and dual-mode sequencing engine supporting time-based, regulation-triggered, and voltage-threshold–based enable timing. Each of its eight MONx inputs samples rail voltages at ≥20 kHz with selectable 2.5-V internal or 3.3-V external reference.

Its ENx/GPOx pins operate as Schmitt-trigger I/Os with V_IT+ = 1.5–1.9 V and V_IT− = 0.9–1.3 V, enabling robust noise immunity during power-up sequencing. Configuration is stored in nonvolatile memory with 100-year retention, and brownout detection triggers internal reset when V_CC drops below 1.71 V with 70–180 mV hysteresis.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage	3.0–3.6 V - powers entire device; supports direct connection to 3.3-V system rails without LDO
Rail Monitoring Resolution	3.2 mV - enables precise detection of ±1% deviations on 3.3-V rails (e.g., 3.3 V ±33 mV)
Sampling Rate	>20 kHz - ensures sub-50-µs response to rail glitches, critical for FPGA/CPU power integrity
I²C Clock Frequency	10–100 kHz - compatible with standard-mode I²C masters; no high-speed mode required
Sequencing Flexibility	Time-, parent-rail-regulation-, or parent-voltage–triggered - allows hierarchical startup (e.g., core before I/O)
UV/OV Threshold Accuracy	±6.8 mV (internal ref) or ±0.2% (external 3.3-V ref) - determines margin for reliable fault detection
Configuration Retention	100 years - eliminates need for external EEPROM or reprogramming at power-on

Pinout & Package

The UCD9080RHBRG4 is housed in a 32-pin QFN package (RHB) with 0.5-mm pitch, 5 mm × 5 mm body, and exposed thermal pad - optimized for thermal dissipation in compact server and telecom modules.

Pin/Terminal	Circuit Role	Design Meaning
VSS (Pin 1)	Ground reference	Primary return path for analog and digital circuits; must be low-impedance connection to system ground plane
VCC (Pin 30)	Supply input	3.3-V power source for internal logic, ADC, and I²C interface; requires local 1-µF ceramic decoupling
MON1–MON8 (Pins 6,7,8,18,19,9,15,16)	Analog voltage inputs	Monitor eight independent rails; each accepts 0–3.3 V (with external divider for >3.3 V rails)
EN1–EN7 (Pins 23,24,11,10,12,13,14)	Digital enable outputs	Active-high/low configurable rail control signals; drive external PMICs or MOSFET gate drivers
EN8/ADDR1/GPO1 (Pin 25)	Multiplexed terminal	Functions as rail 8 enable, I²C address bit A1, or general-purpose output - selected via configuration
ADDR2–ADDR4/GPO2–GPO4 (Pins 26,27,28)	I²C address / GPO	Set 7-bit I²C address (0x60–0x6F) at reset; repurposed as sequenced GPOs post-initialization
SCL/SDA (Pins 22/21)	I²C interface	Standard-mode bidirectional bus; require 3.3-V pullups (typically 4.7 kΩ) for proper signal integrity
RST (Pin 5)	Asynchronous reset input	Drives all EN/GPO pins to high-impedance state for ~4–5 ms; used for system-level recovery

Key Features

Feature	Design Value
Per-rail UV/OV glitch detection	Identifies transient faults down to 50 µs duration - prevents false trips from switching noise
Configurable rail shutdown dependencies	Enables cascaded shutdown (e.g., disable DDR rail if memory controller rail fails)
Timestamped alarm logging	Records exact time of sustained UV/OV events - aids root-cause analysis in field-deployed systems
Flexible enable polarity	Supports both active-high and active-low power supplies - eliminates need for external inverters
ROSC pin for frequency calibration	100-kΩ pullup to VCC sets oscillator drift <±100 ppm/°C - ensures stable sampling rate across temperature

Applications

Telecom Switch Power Management	Server CPU Core Sequencing
Use Scenario: Sequencing multiple DC/DC converters powering line cards, DSPs, and PHYs in carrier-grade switches. IC Role / Device Role / Timing Role: Central sequencer enforcing strict startup order (e.g., 12-V bias before 3.3-V logic) and real-time monitoring of 48-V backplane-derived rails. Use Value: Prevents latch-up and inrush current conflicts by ensuring dependent rails achieve regulation before enabling downstream loads.	Use Scenario: Controlling power-up sequence of CPU core, I/O, memory, and auxiliary rails in dual-socket x86 servers. IC Role / Device Role / Timing Role: Monitors VDDIO and VDDQ with 3.2-mV resolution while triggering VDDCORE enable only after VDDIO reaches 95% regulation window. Use Value: Eliminates boot failures caused by out-of-spec voltage ramp rates or premature enable assertion.
Network Equipment Supervisor	Test Equipment Power Control
Use Scenario: Managing redundant 5-V and 12-V supplies in enterprise routers with failover capability. IC Role / Device Role / Timing Role: Detects sustained undervoltage on primary 5-V rail and initiates automatic switchover to backup supply via GPO-controlled OR-ing FETs. Use Value: Achieves sub-10-ms switchover without host processor intervention - meets carrier-class uptime requirements.	Use Scenario: Coordinating power delivery to DUT (device under test) and measurement circuitry in automated test systems. IC Role / Device Role / Timing Role: Generates synchronized enable pulses and reset signals to ensure DUT powers up only after reference supplies stabilize. Use Value: Reduces test false-fail rate by eliminating marginal voltage conditions during initialization.

Telecom Switch Power Management

Server CPU Core Sequencing

Use Scenario: Sequencing multiple DC/DC converters powering line cards, DSPs, and PHYs in carrier-grade switches.

IC Role / Device Role / Timing Role: Central sequencer enforcing strict startup order (e.g., 12-V bias before 3.3-V logic) and real-time monitoring of 48-V backplane-derived rails.

Use Value: Prevents latch-up and inrush current conflicts by ensuring dependent rails achieve regulation before enabling downstream loads.

Use Scenario: Controlling power-up sequence of CPU core, I/O, memory, and auxiliary rails in dual-socket x86 servers.

IC Role / Device Role / Timing Role: Monitors VDDIO and VDDQ with 3.2-mV resolution while triggering VDDCORE enable only after VDDIO reaches 95% regulation window.

Use Value: Eliminates boot failures caused by out-of-spec voltage ramp rates or premature enable assertion.

Network Equipment Supervisor

Test Equipment Power Control

Use Scenario: Managing redundant 5-V and 12-V supplies in enterprise routers with failover capability.

IC Role / Device Role / Timing Role: Detects sustained undervoltage on primary 5-V rail and initiates automatic switchover to backup supply via GPO-controlled OR-ing FETs.

Use Value: Achieves sub-10-ms switchover without host processor intervention - meets carrier-class uptime requirements.

Use Scenario: Coordinating power delivery to DUT (device under test) and measurement circuitry in automated test systems.

IC Role / Device Role / Timing Role: Generates synchronized enable pulses and reset signals to ensure DUT powers up only after reference supplies stabilize.

Use Value: Reduces test false-fail rate by eliminating marginal voltage conditions during initialization.

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-supply sequencing applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
UCD90100RGCT	12-channel, higher-resolution 12-bit ADC, supports SMBus/PMBus v1.2, larger config memory	Required for systems with >8 rails or needing PMBus telemetry (e.g., data center PSUs)	Select when expanding beyond 8 rails or requiring industry-standard PMBus command set
TPS65400RGER	Integrated 4-channel buck + LDO PMIC with embedded sequencer; no external I²C master needed	Best for cost-sensitive, space-constrained designs where power conversion and sequencing are co-located	Select when combining regulation and sequencing in one chip reduces BOM count and layout area

Compared with UCD9080RHBRG4, UCD90100RGCT adds channel count and protocol flexibility but increases complexity and cost; TPS65400RGER integrates power stages but lacks UCD9080RHBRG4's precision rail monitoring and independent sequencing granularity.

Availability

UCD9080RHBRG4 is available at Aetrix Electronics and suitable for telecom switches, server motherboards, and network equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for UCD9080RHBRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of heritage in high-reliability industrial and communications ICs.

The UCD9080RHBRG4 belongs to TI's UCD power sequencer family, designed specifically for complex multi-rail systems where deterministic startup timing, precise voltage monitoring, and fault-responsive shutdown are mandatory - not just desirable.

FAQ

What is the maximum number of voltage rails the UCD9080RHBRG4 can monitor and sequence?

The UCD9080RHBRG4 monitors and sequences up to eight independent voltage rails using its MON1–MON8 analog inputs and EN1–EN8 digital enable outputs. Each rail supports fully independent configuration of UV/OV thresholds, regulation windows, and sequencing dependencies - verified in the SLVS692E datasheet Section 1.1 and Table 1. This makes UCD9080RHBRG4 ideal for systems like multi-core processors or FPGA-based platforms requiring granular power control.

Does the UCD9080RHBRG4 require an external clock or memory to operate?

No, the UCD9080RHBRG4 operates autonomously without external clock or memory. Its internal oscillator (calibrated via ROSC pin with 100-kΩ pullup) drives the 10-bit SAR ADC and sequencing engine, and configuration parameters are retained in on-chip nonvolatile memory for 100 years - confirmed in Electrical Characteristics Section 6.5 and Functional Description Section 8.1. This eliminates BOM cost and layout complexity associated with external components, simplifying design of UCD9080RHBRG4-based power systems.

How does the UCD9080RHBRG4 handle brownout conditions during operation?

The UCD9080RHBRG4 features an integrated brownout detector that asserts internal reset when V_CC falls below 1.71 V (with 70–180 mV hysteresis), holding ENx/GPOx pins in high-impedance state for ~4–5 ms - detailed in Absolute Maximum Ratings Section 6.1 and Figure 4. Upon recovery, it re-executes the full sequencer configuration, ensuring deterministic restart behavior. This protects downstream circuitry from undefined states during unstable supply conditions - a critical capability for UCD9080RHBRG4 deployments in telecom infrastructure.

Can the UCD9080RHBRG4's ENx pins drive external MOSFET gates directly?

The UCD9080RHBRG4's ENx pins are digital outputs rated for ±6 mA sink/source (V_OL ≤ 0.6 V, V_OH ≥ V_CC – 0.6 V at 3 V), sufficient to drive logic-level MOSFET gates or enable inputs of external PMICs - per Electrical Characteristics Section 6.7. However, for high-side N-channel MOSFETs requiring gate voltage above V_CC, a dedicated gate driver IC is required. The UCD9080RHBRG4 datasheet explicitly recommends external buffering for such cases, ensuring safe and reliable interfacing.

What I²C address range does the UCD9080RHBRG4 support, and how is it configured?

The UCD9080RHBRG4 supports seven-bit I²C addresses from 0x60 to 0x6F, set by sampling ADDR1–ADDR4 (EN8/ADDR1/GPO1, ADDR2/GPO2, ADDR3/GPO3, ADDR4/GPO4) during reset - shown in Figure 8 and described in Section 9.1. External pullup/pulldown resistors (no internal bias) determine logic levels; after reset, these pins become configurable GPOs. This flexible addressing allows up to 16 UCD9080RHBRG4 devices on a single I²C bus, essential for large-scale server or storage systems.

UCD9080RHBRG4 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 32-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Discontinued at Digi-Key

Programmable:: Not Verified

Type:: Sequencer

Number of Voltages Monitored:: 8

Voltage - Threshold:: Adjustable/Selectable

Output:: -

Reset:: Active High/Active Low

Reset Timeout:: 2µs Minimum

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 32-VQFN (5x5)

UCD9080RHBRG4 FAQ

1.How can I place an order for UCD9080RHBRG4 through Aetrix?

Please submit a Request for Quotation (RFQ) for UCD9080RHBRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for UCD9080RHBRG4 reliable?

The price and inventory of UCD9080RHBRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCD9080RHBRG4 is usually 5 days.

3.What payment methods are accepted for UCD9080RHBRG4?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCD9080RHBRG4 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for UCD9080RHBRG4?

UCD9080RHBRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your UCD9080RHBRG4 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for UCD9080RHBRG4?

For technical support, including UCD9080RHBRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCD9080RHBRG4 requirements.

6.How does Aetrix verify that UCD9080RHBRG4 is sourced from the original manufacturer or authorized distributors?

All UCD9080RHBRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCD9080RHBRG4 meets industry standards.

7.What is the process for return or replacement of UCD9080RHBRG4?

All UCD9080RHBRG4 units undergo pre-shipment inspection (PSI). If there is an issue with UCD9080RHBRG4, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The UCD9080RHBRG4 part is unused and in its original packaging.

Return procedure for UCD9080RHBRG4:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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