Texas Instruments UCD9090ARGZR
- Part No.:
- UCD9090ARGZR
- Manufacturer:
- Texas Instruments
- Category:
- Supervisors
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
UCD9090ARGZR.pdf
- Description:
- IC SUPERVISOR 10 CHANNEL 48VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UCD9090ARGZR from Texas Instruments is a 10-rail PMBus/I²C-addressable power supply sequencer and monitor with ACPI support, integrating a 12-bit ADC (2.5 V ±0.5% internal reference), 400 μs per-rail sampling, four programmable UV/OV thresholds per rail, nonvolatile fault logging (26 entries), and closed-loop margining for all 10 rails. It serves in server power management systems requiring precise, coordinated startup/shutdown of CPU, memory, and I/O voltage domains.
For engineers reviewing the UCD9090ARGZR datasheet, UCD9090ARGZR pinout, UCD9090ARGZR application, or UCD9090ARGZR equivalent, key selection criteria include rail count (10), ADC resolution (12-bit), PMBus v1.1 compliance, VQFN-48 package compatibility, and support for pin-selected low-power states per ACPI specification.
Technical Context
The UCD9090ARGZR implements a deterministic sequencing engine with time-, rail-, and GPI-triggered dependencies, enabling precise control of power-up/down order across heterogeneous rails. Its 12-bit ADC samples all 10 monitored rails every 400 μs using a 2.5-V internal reference with ±0.5% accuracy over 0°C–125°C.
It supports dual-mode PWM generation: eight FPWM outputs (15.26 kHz–125 MHz) for synchronizing switch-mode supplies, and two GPI-capable PWMs (0.93 Hz–7.81 MHz) for margining control. Fault response is configurable via Boolean logic GPOs and cascaded fault coordination across multiple devices.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Rail count | 10 independent voltage rails monitored and sequenced, each with dedicated enable, margining, and UV/OV threshold configuration. |
| ADC resolution & speed | 12-bit resolution with 400 μs full-rail sampling cycle - enables real-time health monitoring without compromising timing-critical sequencing. |
| Internal reference | 2.5 V ±0.5% over 0°C–125°C - eliminates need for external precision reference and ensures consistent ADC accuracy across temperature. |
| PMBus interface | Compliant with PMBus v1.1 and SMBus 1.1; supports 10–400 kHz operation - enables interoperability with standard power management hosts and telemetry systems. |
| Margining capability | Closed-loop margining on all 10 rails using FPWM outputs - allows automated four-corner testing (min/max voltage stress) without external DACs or manual adjustment. |
| Nonvolatile logging | Stores up to 26 fault detail entries with timestamps in on-chip flash - supports post-failure root-cause analysis without host intervention or external memory. |
| Operating temperature | –40°C to +110°C ambient - qualified for industrial and telecom infrastructure environments with extended thermal cycling requirements. |
Pinout & Package
The UCD9090ARGZR is housed in a 48-pin VQFN (RGZ) package measuring 7.0 mm × 7.0 mm with exposed thermal pad. Pin functions are validated per TI SLVSDD7B datasheet Rev. March 2022.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MON1–MON10 | Analog monitor input | 0–2.5 V input range for rail voltage sensing; MON11 supports 0.2–2.5 V for bias-sensitive nodes. |
| FPWM1–FPWM8 | Configurable PWM output | 15.26 kHz–125 MHz frequency range; used for closed-loop margining or multi-phase clock synchronization. |
| PWM1/GPI1, PWM2/GPI2 | Programmable I/O | Supports both margining PWM (0.93 Hz–7.81 MHz) and general-purpose input for sequencing triggers. |
| PMBus_CLK / PMBus_DATA | PMBus slave interface | Open-drain, 3.3-V referenced; supports 10–400 kHz communication for configuration, telemetry, and fault reporting. |
| GPIO1–GPIO4, GPIO13–GPIO17 | General-purpose I/O | Configurable as inputs (GPI) for ACPI state selection or outputs (GPO) with Boolean logic for fault coordination. |
| V33A / V33D / DVSS / AVSS1 / AVSS2 | Power and ground | Separate analog/digital 3.3-V supplies and dedicated ground planes minimize noise coupling into ADC and sequencing logic. |
Key Features
| Feature | Design Value |
|---|---|
| Pin-selected rail states | Uses up to 3 GPIs to define 8 discrete system power states (e.g., S0–S5 per ACPI), enabling hardware-controlled low-power modes without host firmware involvement. |
| Cascadable fault coordination | Propagates fault signals across multiple UCD9090ARGZR devices via dedicated cascade pins, ensuring synchronized shutdown of interdependent power domains. |
| Boolean logic GPOs | 10 programmable logic outputs with configurable inputs (GPIs, POWER_GOOD, faults); supports custom fault response policies without MCU intervention. |
| Runtime clock generator | Generates independent PWM clocks (15.26 kHz–125 MHz) for synchronizing multiple DC/DC controllers - eliminates timing skew in multi-phase power stages. |
| JTAG + PMBus dual debug | Full JTAG access for boundary scan and firmware debugging, plus PMBus for runtime configuration and telemetry - supports both pre-deployment validation and field diagnostics. |
Applications
| Server Power Management | Telecom Line Card Sequencing |
|---|---|
Use Scenario: Coordinating power-up sequence of CPU core (0.8 V), memory (1.2 V), I/O (3.3 V), and auxiliary rails in 1U rack servers. IC Role / Device Role / Timing Role: Centralized sequencer enforcing strict turn-on delays, dependency chains, and POWER_GOOD validation before releasing reset to processors. Use Value: Prevents latch-up and inrush current overload by ensuring rails reach regulation before downstream logic activation - verified via 400 μs per-rail sampling and 12-bit ADC accuracy. | Use Scenario: Managing hot-swap sequencing and fault isolation on modular telecom line cards with mixed ASIC/FPGA power domains. IC Role / Device Role / Timing Role: Monitor-and-respond controller that detects overvoltage on 12-V bias rail and initiates immediate shutdown of dependent 3.3-V and 1.8-V supplies. Use Value: Achieves <100 μs fault-to-shutdown latency using GPI-triggered response and nonvolatile fault logging - critical for meeting GR-1089-CORE surge immunity requirements. |
| Industrial PLC Backplane | ATE Power Subsystem |
Use Scenario: Enabling low-power sleep mode in programmable logic controllers by disabling non-essential I/O rails while maintaining real-time clock and watchdog functionality. IC Role / Device Role / Timing Role: ACPI-compliant state manager using Pin-Selected Rail States (3 GPI inputs) to map hardware switch positions to predefined rail enable/disable patterns. Use Value: Reduces system standby power by >65% without firmware updates - validated across –40°C to +85°C operating range with no calibration drift. | Use Scenario: Performing four-corner voltage margining during production test of high-speed ADC/DAC modules requiring simultaneous 1.8-V, 3.3-V, and 5-V rail stress. IC Role / Device Role / Timing Role: Closed-loop margining engine adjusting each rail's output via FPWM feedback to hit ±0.5% target tolerance under load variation. Use Value: Eliminates external margining DACs and reduces test setup complexity - achieves 10-rail margining in <200 ms using on-chip 12-bit ADC and FPWM outputs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power supply sequencing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCD90160RGZR | 16-rail capacity, higher pin count (64-pin VQFN), supports more complex dependency trees and additional GPIOs. | Suitable for multi-ASIC systems requiring >10 rails or advanced fault propagation logic. | Select UCD90160RGZR when scaling beyond 10 rails or needing enhanced Boolean logic depth; UCD9090ARGZR remains optimal for cost-sensitive 10-rail deployments. |
| LM90610QMHX/NOPB | 10-rail sequencer with SPI interface only (no PMBus), lower integration (no FPWM, no cascading fault pins). | Targeted at automotive infotainment where SPI is preferred and cascading is unnecessary. | Choose LM90610QMHX/NOPB only if SPI interface and AEC-Q100 qualification are mandatory; UCD9090ARGZR provides broader feature set for industrial/server use. |
Compared with UCD90160RGZR, the UCD9090ARGZR offers identical sequencing architecture and PMBus v1.1 compliance but trades rail count for smaller footprint and lower BOM cost; versus LM90610QMHX/NOPB, it delivers superior telemetry, margining, and fault coordination - making it the preferred choice for high-reliability, multi-rail infrastructure systems.
Availability
UCD9090ARGZR is available at Aetrix Electronics and suitable for server power management, telecom line card sequencing, and industrial PLC backplane applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for UCD9090ARGZR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and power management technologies, with leadership in high-reliability industrial and infrastructure solutions.
The UCD9090ARGZR belongs to TI's Fusion Digital Power™ sequencer family, designed specifically for intelligent, PMBus-based power system health monitoring and coordinated multi-rail sequencing in datacenter, telecom, and industrial equipment.
FAQ
What is the maximum number of voltage rails the UCD9090ARGZR can monitor and sequence?
The UCD9090ARGZR monitors and sequences up to 10 independent voltage rails. Each rail supports programmable undervoltage and overvoltage thresholds, power-good detection, and closed-loop margining. The device uses MON1–MON10 analog inputs for rail sensing, with MON11 reserved for auxiliary monitoring such as temperature or bias voltages.
Does the UCD9090ARGZR support ACPI-compliant low-power states?
Yes, the UCD9090ARGZR implements Pin-Selected Rail States using up to three GPI inputs to define eight discrete power states, directly supporting hardware-enforced ACPI S0–S5 modes. This enables automatic rail enable/disable patterns for sleep, suspend, and hibernate without host processor involvement - a key requirement for server and industrial control platforms.
What interfaces does the UCD9090ARGZR provide for configuration and telemetry?
The UCD9090ARGZR supports both PMBus v1.1 (via PMBus_CLK/PMBus_DATA pins) and JTAG for configuration and diagnostics. PMBus enables runtime telemetry, fault logging, and parameter updates using standard commands; JTAG provides full boundary-scan access and firmware-level debugging. TI's Fusion Digital Power Designer GUI integrates with both interfaces for intuitive setup.
How does the UCD9090ARGZR handle fault events and logging?
The UCD9090ARGZR stores up to 26 fault detail entries with timestamps in on-chip nonvolatile flash memory. Fault responses - including immediate shutdown, sequenced off, or coordinated cascade actions - are user-configurable via Boolean logic GPOs. Each fault log includes rail ID, timestamp, threshold violation type (UV/OV), and associated GPI/GPO state at time of event.
What is the ADC performance specification of the UCD9090ARGZR?
The UCD9090ARGZR features a 12-bit ADC with 2.5 V ±0.5% internal reference over 0°C–125°C, integral nonlinearity (INL) of ±4 LSB, differential nonlinearity (DNL) of ±2 LSB, and full 10-rail sampling completed every 400 μs. Input impedance is 8 MΩ for MON1–MON10, ensuring minimal loading on sensitive power rails during monitoring.
UCD9090ARGZR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Sequencer
- Number of Voltages Monitored:
- 10
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- -
- Reset:
- Active Low
- Reset Timeout:
- 2µs Minimum
- Operating Temperature:
- -40°C ~ 110°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VQFN (7x7)
UCD9090ARGZR FAQ
1.How can I place an order for UCD9090ARGZR through Aetrix?
Please submit a Request for Quotation (RFQ) for UCD9090ARGZR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCD9090ARGZR reliable?
The price and inventory of UCD9090ARGZR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCD9090ARGZR is usually 5 days.
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UCD9090ARGZR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCD9090ARGZR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCD9090ARGZR?
For technical support, including UCD9090ARGZR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCD9090ARGZR requirements.
6.How does Aetrix verify that UCD9090ARGZR is sourced from the original manufacturer or authorized distributors?
All UCD9090ARGZR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCD9090ARGZR meets industry standards.
7.What is the process for return or replacement of UCD9090ARGZR?
All UCD9090ARGZR units undergo pre-shipment inspection (PSI). If there is an issue with UCD9090ARGZR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCD9090ARGZR part is unused and in its original packaging.
Return procedure for UCD9090ARGZR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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