NXP Semiconductors UDA1341TS/N1,518
- Part No.:
- UDA1341TS/N1,518
- Manufacturer:
- NXP Semiconductors
- Category:
- CODECS
- Package:
- 28-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
UDA1341TS/N1,518.pdf
- Description:
- IC AUDIO CODEC 20BIT 28SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,296
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UDA1341TS/N1,518 from NXP Semiconductors is a single-chip stereo audio CODEC integrating ADC and DAC with digital sound processing, operating from a 3.0 V supply, supporting 256fs/384fs/512fs system clocks, and delivering 100 dB SNR in double-differential ADC mode for MiniDisc home stereo and portable applications.
For engineers reviewing the UDA1341TS/N1,518 datasheet, UDA1341TS/N1,518 pinout, UDA1341TS/N1,518 application, or UDA1341TS/N1,518 equivalent, key selection considerations include its L3-interface programmability, dual-input analog front end with PGA and digital AGC on channel 2, I²S/MSB/LSB data format flexibility, and FSDAC architecture eliminating need for external analog post-filtering.
Technical Context
The UDA1341TS/N1,518 implements sigma-delta conversion with 128× oversampling in both ADC and DAC paths, using a 3rd-order noise shaper (DAC) and 3rd-order Ritchie-coder modulators (ADC). Its decimation filter provides 108 dB dynamic range and ±0.05 dB passband ripple; interpolation filter delivers ±0.03 dB ripple and >50 dB stopband attenuation.
Digital signal processing includes programmable volume (−∞ to 0 dB in 1 dB steps), bass boost (0–24 dB), treble (0–12 dB), de-emphasis (32/44.1/48 kHz), soft mute, and peak detection with configurable position-fully controlled via 3-wire L3-interface (L3DATA/L3CLOCK/L3MODE) with address/data transfer modes and extended register access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 2.4–3.6 V for ADC/DAC/digital supplies - enables single 3.0 V rail operation with 12.5 mA ADC and 7.0 mA DAC active current. |
| ADC SNR | 100 dB (A-weighted, double-differential mode) - supports high-fidelity microphone input capture without external preamp. |
| DAC SNR | 100 dB (A-weighted) - delivers line-level output (900 mV RMS) directly drivable by integrated FSDAC op-amps. |
| THD+N (DAC) | −91 dB (0 dBFS) - ensures low distortion playback even at full scale. |
| PGA Gain Range | −3 to +27 dB in 0.5 dB steps - allows precise microphone sensitivity matching via L3-interface. |
| AGC Control | Configurable attack/decay time and output level - enables automatic record-level optimization for portable MD recording. |
| Data Interface | I²S, MSB-justified (up to 20-bit), LSB-justified (16/18/20-bit), and hybrid MSB-out/LSB-in formats - ensures compatibility with diverse host MCUs and DSPs. |
Pinout & Package
UDA1341TS/N1,518 is housed in a plastic shrink small outline package (SSOP28) with 28 leads and 5.3 mm body width (SOT341-1), optimized for compact audio subsystem layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINL1 / VINR1 | ADC1 stereo line input | Supports 1–2 VRMS signals with selectable 0/6 dB gain; requires 12 kΩ series resistor for 2 VRMS operation. |
| VINL2 / VINR2 | ADC2 stereo mic input with PGA | Accepts low-level microphone signals; PGA gain set via L3-interface from −3 to +27 dB. |
| DATAI / DATAO | Digital audio data I/O | Supports I²S, MSB/LSB-justified formats up to 20 bits; bit clock ≤64× word select frequency. |
| L3DATA / L3CLOCK / L3MODE | L3 serial control interface | 3-wire bus for programming all DSP features, power states, and register reads (e.g., peak level). |
| QMUTE | Hardware quick-mute input | Asynchronous hard mute: HIGH forces DAC output to zero instantly, independent of L3 control. |
| OVERFL | ADC overflow indicator | Active-HIGH pulse ≥512fs duration when left/right channel exceeds −1.16 dBFS - enables real-time clipping prevention. |
Key Features
| Feature | Design Value |
|---|---|
| Digital AGC with programmable timing | Enables hands-free microphone recording in variable acoustic environments via L3-controlled attack/decay/output level. |
| FSDAC architecture | Eliminates need for external analog reconstruction filter while achieving 100 dB SNR and low jitter sensitivity. |
| Dual ADC input configurations | Supports simultaneous line + mic inputs with digital mixing, or double-differential mode for 100 dB SNR ADC performance. |
| L3-interface extended addressing | Allows full configuration of 5-bit mixer coefficients, 5-bit AGC parameters, and 3-bit extended register selection. |
| DC cancellation filter | Removes input offset drift in ADC path; configurable via STATUS register with 279 ms startup delay when enabled. |
Applications
| MiniDisc Home Stereo System | Portable MD Recorder |
|---|---|
Use Scenario: Integrated audio processing in MiniDisc deck for playback and recording with CD-quality fidelity. IC Role / Device Role / Timing Role: Primary stereo CODEC handling analog line/mic input digitization, digital signal processing (de-emphasis, tone control), and DAC-based line output generation. Use Value: Single-chip solution reduces BOM count and PCB area while meeting MD specification requirements for SNR (>97 dB) and THD+N (<−80 dB). | Use Scenario: Battery-powered MD recorder requiring low-power, high-SNR audio capture and playback. IC Role / Device Role / Timing Role: Dual-path audio processor managing mic pre-amplification (via PGA), automatic gain control, and low-distortion DAC output under 3.0 V operation. Use Value: 12.5 mA ADC + 7.0 mA DAC active current and power-down modes (6.0 mA ADC, 50 μA DAC) extend battery life without compromising audio quality. |
| Notebook PC Audio Subsystem | Digital Video Camera Audio |
Use Scenario: Embedded audio codec for notebook PCs needing flexible input routing and software-controllable tone processing. IC Role / Device Role / Timing Role: Stereo ADC/DAC with L3-interface programmability enabling OS-level volume, bass/treble, and mute control via microcontroller. Use Value: I²S/MSB/LSB format support ensures interoperability with Intel HD Audio or custom SoC interfaces; 20-bit resolution accommodates high-fidelity capture. | Use Scenario: Compact audio acquisition in digital video cameras where size and power are critical. IC Role / Device Role / Timing Role: Mic-input-focused CODEC with digital AGC and overload detection for reliable spoken-word and ambient audio capture during video recording. Use Value: OVERFL pin provides hardware-level clipping alert; AGCSTAT signal enables LED feedback or firmware gain adjustment - improving usability in handheld operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar audio CODEC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UDA1344TS | Partially pin-compatible SSOP28 successor with enhanced digital mixer and improved AGC algorithm; same 3.0 V supply and L3-interface. | Targets newer MD designs requiring higher integration density and lower THD+N (−93 dB vs −91 dB). | Select UDA1344TS when upgrading legacy UDA1341TS designs for improved dynamic range and mixer flexibility. |
| AK4531VN | 24-bit stereo CODEC in TSSOP28; supports I²S/PCM only (no LSB/MSB hybrid); requires separate 1.8 V digital supply. | Suitable for non-MD consumer audio where 24-bit resolution and lower power (8.5 mA total) outweigh format flexibility. | Choose AK4531VN for new designs prioritizing resolution and ultra-low power over L3-interface simplicity and multi-format compatibility. |
Compared with UDA1341TS/N1,518, UDA1344TS offers incremental improvements in AGC and mixer capability within identical footprint and control architecture, while AK4531VN trades L3 programmability and format versatility for higher resolution and lower power - making UDA1341TS/N1,518 optimal for cost-sensitive, L3-based MD and portable audio systems requiring proven reliability.
Availability
UDA1341TS/N1,518 is available at Aetrix Electronics and suitable for MiniDisc home stereo systems, portable MD recorders, notebook PC audio subsystems, and digital video camera audio acquisition requiring stable component supply and long-term lifecycle support.
Supply support for UDA1341TS/N1,518 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer electronics.
The UDA1341TS/N1,518 belongs to NXP's economy audio CODEC product line, designed specifically for cost-optimized MiniDisc and portable audio applications requiring integrated analog front end, digital signal processing, and minimal external components.
FAQ
What is the maximum supported word length for the UDA1341TS/N1,518 digital audio interface?
The UDA1341TS/N1,518 supports up to 20-bit word length in I²S-bus and MSB-justified formats, and 16/18/20-bit word lengths in LSB-justified and hybrid MSB-output/LSB-input configurations. This flexibility allows seamless integration with host processors offering varying data-width capabilities while maintaining compatibility with legacy 16-bit audio pipelines.
Does the UDA1341TS/N1,518 require external analog filtering on its DAC output?
No, the UDA1341TS/N1,518 does not require external analog post-filtering due to its Filter Stream Digital-to-Analog Converter (FSDAC) architecture. The integrated FSDAC inherently performs reconstruction filtering, delivering a clean 900 mV RMS line-level output directly suitable for driving headphones or line inputs without additional passive components.
How is microphone input gain controlled on the UDA1341TS/N1,518?
Microphone input gain on the UDA1341TS/N1,518 is controlled via the Programmable Gain Amplifier (PGA) on ADC channel 2, which is programmed through the L3-interface. The PGA offers seven discrete gain settings: −3, 0, 3, 9, 15, 21, and 27 dB, enabling precise matching to diverse microphone sensitivities without external amplification circuitry.
What system clock frequencies does the UDA1341TS/N1,518 support?
The UDA1341TS/N1,518 supports three selectable system clock frequencies: 256fs, 384fs, and 512fs - where fs is the audio sample rate (e.g., 44.1 kHz). These options are configured via the STATUS register's SC1/SC0 bits and must be locked in frequency to the digital interface signals (BCK/WS) for stable sigma-delta operation.
Can the UDA1341TS/N1,518 perform simultaneous line and microphone input recording?
Yes, the UDA1341TS/N1,518 supports simultaneous line and microphone input recording through its digital mixer function. In ADC1+ADC2 mixer mode, outputs from both stereo ADC channels (including PGA and digital AGC on channel 2) are mixed with programmable coefficients (0 to −∞ dB in 1.5 dB steps), enabling blended audio capture without external summing circuitry.
UDA1341TS/N1,518 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 28-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Stereo Audio
- Data Interface:
- Serial
- Resolution (Bits):
- 20 b
- Number of ADCs / DACs:
- 4 / 2
- Sigma Delta:
- Yes
- S/N Ratio, ADCs / DACs (db) Typ:
- 100 / 100
- Dynamic Range, ADCs / DACs (db) Typ:
- -
- Voltage - Supply, Analog:
- 2.4V ~ 3.6V
- Voltage - Supply, Digital:
- 2.4V ~ 3.6V
- Operating Temperature:
- -20°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SSOP
UDA1341TS/N1,518 FAQ
1.How can I place an order for UDA1341TS/N1,518 through Aetrix?
Please submit a Request for Quotation (RFQ) for UDA1341TS/N1,518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UDA1341TS/N1,518 reliable?
The price and inventory of UDA1341TS/N1,518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UDA1341TS/N1,518 is usually 5 days.
3.What payment methods are accepted for UDA1341TS/N1,518?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UDA1341TS/N1,518 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UDA1341TS/N1,518?
UDA1341TS/N1,518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UDA1341TS/N1,518 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UDA1341TS/N1,518?
For technical support, including UDA1341TS/N1,518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UDA1341TS/N1,518 requirements.
6.How does Aetrix verify that UDA1341TS/N1,518 is sourced from the original manufacturer or authorized distributors?
All UDA1341TS/N1,518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UDA1341TS/N1,518 meets industry standards.
7.What is the process for return or replacement of UDA1341TS/N1,518?
All UDA1341TS/N1,518 units undergo pre-shipment inspection (PSI). If there is an issue with UDA1341TS/N1,518, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UDA1341TS/N1,518 part is unused and in its original packaging.
Return procedure for UDA1341TS/N1,518:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UDA1341TS/N1,518 Tags

-
NAU88C22YG
Nuvoton Technology Corporation

-
TLV320AIC3100IRHBR
Texas Instruments

-
DA7212-01UM2
Renesas

-
NAU8810YG
Nuvoton Technology Corporation

-
DA7218-00U32
Renesas

-
CMX655DQ6-TR1K
CML Micro

-
SGTL5000XNLA3
NXP Semiconductors

-
TLV320AIC3104IRHBR
Texas Instruments

-
MAX9867EWV+T
Analog Devices Inc./Maxim Integrated

-
MAX9860ETG+T
Analog Devices Inc./Maxim Integrated

-
TLV320AIC3106IRGZR
Texas Instruments

-
SGTL5000XNLA3R2
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

