NXP Semiconductors UDA1345TS/N2,112
- Part No.:
- UDA1345TS/N2,112
- Manufacturer:
- NXP Semiconductors
- Category:
- CODECS
- Package:
- 28-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
UDA1345TS/N2,112.pdf
- Description:
- IC AUDIO CODEC 28-SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UDA1345TS/N2,112 from NXP Semiconductors is a low-power stereo audio CODEC integrating sigma-delta ADC and DAC with digital interpolation/decimation filters, 2.4–3.6 V supply operation, 8–100 kHz sampling support, and dual control modes (L3 microcontroller or static pin). It delivers 96 dB SNR (DAC), −85 dB THD+N at 44.1 kHz, and drives line outputs directly-used in portable digital audio recorders and playback devices.
For engineers reviewing the UDA1345TS/N2,112 datasheet, UDA1345TS/N2,112 pinout, UDA1345TS/N2,112 application, or UDA1345TS/N2,112 equivalent, this page provides verified technical context, validated pin functions, confirmed L3/static mode behavior, real-world power consumption data (36–64 mW), and precise interface compatibility across I2S, MSB-justified, and LSB-justified formats up to 24 bits.
Technical Context
The UDA1345TS/N2,112 implements a 5th-order sigma-delta ADC with 64× oversampling and integrated DC cancellation filter, plus a 3rd-order noise shaper DAC operating at 128fs driving a Filter Stream DAC (FSDAC) output stage. Its decimation and interpolation filters achieve >114 dB dynamic range and ±0.05 dB passband ripple.
It supports slave-mode digital audio interfaces only, requiring external system clocks synchronized to WS/BCK (fBCK ≤ 128 × fWS). Control is implemented via either L3-bus (8-bit address + data transfers, LSB-first) or static pins-MC1/MC2 determine mode, while MP2–MP5 configure de-emphasis, mute, gain, and format selection without firmware.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 2.4–3.6 V for all analog/digital rails-enables direct battery operation in 3 V systems without regulation. |
| Sampling Rate | 8–100 kHz (512fs mode limited to 8–55 kHz)-covers voice, CD, and high-res audio playback/recording. |
| DAC SNR | 90–100 dB A-weighted at 44.1 kHz-meets line-output fidelity requirements without external post-filtering. |
| ADC THD+N | −80 to −85 dB at 0 dBFS, 44.1 kHz-supports clean recording of 1–2 VRMS analog inputs. |
| Power Consumption | 36 mW (playback only), 46 mW (record only), 64 mW (full record+playback)-optimized for battery life in portable designs. |
| Digital Interface | I2S, MSB-justified (≤24 bits), LSB-justified (16/18/20 bits), and hybrid formats-interoperates with common audio SoCs and DSPs. |
| Control Modes | L3-bus (address/data transfer, register-level control) or static pin (MP2–MP5 logic levels)-no firmware dependency for basic configuration. |
Pinout & Package
UDA1345TS/N2,112 is housed in a plastic shrink small outline package (SSOP28) with 5.3 mm body width (SOT341-1), optimized for compact portable audio PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VSSA(ADC) (1) | ADC analog ground | Separate ground return for ADC section-critical for noise isolation in mixed-signal layout. |
| VDDA(ADC) (2) | ADC analog supply | Dedicated 2.4–3.6 V rail for ADC-decoupling required to maintain >90 dB SNR performance. |
| VINL/VINR (3,5) | Stereo analog inputs | Accept 1–2 VRMS signals via external 12 kΩ series resistor and internal 0/6 dB gain switch. |
| SYSCLK (12) | System clock input | 256fs/384fs/512fs master clock-must be phase-locked to BCK/WS for jitter-free conversion. |
| BCK/WS/DATAI/DATAO (16–19) | I2S/serial interface | 5 V-tolerant, Schmitt-triggered-compatible with 3.3 V logic controllers without level shifters. |
| MP1–MP5 (9,13–15,20) | Multi-purpose control | Configure gain, mute, de-emphasis, format, and power mode in static pin mode-no software needed. |
| VOUTL/VOUTR (26,24) | Stereo line outputs | Direct-drive capability (900 mVRMS) into 5 kΩ loads-eliminates need for external op-amps. |
Key Features
| Feature | Design Value |
|---|---|
| Filter Stream DAC (FSDAC) | Current-source-based reconstruction with inherent filtering-achieves 96 dB SNR and eliminates external post-filter components. |
| DC Cancellation Filter | Configurable IIR high-pass filter (enabled via L3-bus)-removes DC offset without affecting audio band integrity. |
| Overload Detection | Hardware flag (OVERFL on MP1) asserts HIGH for ≥512fs cycles when digital output exceeds −1.16 dBFS-enables automatic AGC in record path. |
| Soft Mute/De-mute | Cosine roll-off/roll-up over 128 samples-prevents audible clicks during DAC power transitions. |
| 5 V-Tolerant Digital I/O | All digital pins accept 0–5 V inputs-simplifies interfacing with legacy 5 V microcontrollers or level-shifting circuits. |
Applications
| Portable Voice Recorder | Digital Audio Player |
|---|---|
Use Scenario: Battery-powered handheld device capturing speech with automatic gain control and low-noise playback. IC Role / Device Role / Timing Role: Stereo ADC digitizes microphone input; DAC converts stored PCM to line-level output; SYSCLK synchronizes to host SoC. Use Value: 96 dB SNR and −85 dB THD+N ensure clear voice capture; 36 mW playback power extends runtime; overload detection enables robust AGC. |
Use Scenario: Compact MP3/WMA player with headphone and line-out capability, supporting multiple sample rates. IC Role / Device Role / Timing Role: DAC reconstructs decoded audio; L3-bus configures de-emphasis (44.1/48 kHz) and volume; static pins allow hardware mute. Use Value: Integrated FSDAC delivers full-scale 900 mVRMS output without external amplifiers; 24-bit I2S support ensures bit-perfect playback fidelity. |
| USB Audio Adapter | Smart Speaker Audio Front-End |
Use Scenario: USB-to-analog converter dongle for PC audio output, requiring plug-and-play compatibility and minimal BOM. IC Role / Device Role / Timing Role: DAC receives I2S from USB audio controller; VDDO powers output op-amps; static pin mode sets fixed format. Use Value: SSOP28 footprint saves board space; 5 V-tolerant DATAO/WS/BCK simplify connection to USB bridge ICs; no external filters reduce component count. |
Use Scenario: Always-on voice assistant device needing low-power wake-on-voice and clean local playback feedback. IC Role / Device Role / Timing Role: ADC monitors far-field mic array; DAC plays TTS responses; L3-bus dynamically adjusts gain and DC filter per acoustic environment. Use Value: 300–800 μA ADC power-down current enables ultra-low standby; configurable 0/6 dB gain optimizes SNR for varying mic sensitivity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar stereo audio CODEC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UDA1344TS/N2,112 | Pin- and function-compatible; includes bass-boost and treble tone controls not present in UDA1345TS/N2,112. | Preferred where analog EQ is required pre-DAC; UDA1345TS/N2,112 lacks these features entirely. | Select UDA1344TS/N2,112 only if tone shaping is needed; otherwise UDA1345TS/N2,112 offers identical core conversion performance at lower complexity. |
| AK4537VN | 24-bit stereo CODEC with 98 dB DAC SNR; requires 5 V analog supply (vs. 2.4–3.6 V for UDA1345TS/N2,112); no static pin mode. | Targets higher-fidelity applications with external LDO; lacks hardware-configurable mode-requires full L3 firmware integration. | Choose AK4537VN for premium SNR and 24-bit resolution; choose UDA1345TS/N2,112 for 3 V battery operation and zero-software configuration flexibility. |
Compared with UDA1344TS/N2,112, the UDA1345TS/N2,112 removes tone controls but retains identical ADC/DAC architecture and power efficiency; versus AK4537VN, it trades 2 dB SNR for 3 V operation and static-pin configurability-making it optimal for cost-sensitive, low-power portable designs without EQ needs.
Availability
UDA1345TS/N2,112 is available at Aetrix Electronics and suitable for portable audio recorders, digital music players, and USB audio adapters requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for UDA1345TS/N2,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and consumer applications, with deep expertise in mixed-signal audio processing.
The UDA1345TS/N2,112 belongs to NXP's economy audio CODEC product line, designed specifically for cost-optimized, battery-powered portable audio equipment requiring integrated ADC/DAC functionality without external filtering or voltage translation.
FAQ
What is the maximum supported sampling frequency for UDA1345TS/N2,112 in 512fs mode?
The UDA1345TS/N2,112 supports sampling frequencies up to 55 kHz when using the 512fs system clock mode. This limitation arises from the internal decimation/interpolation architecture-higher rates (up to 100 kHz) require 256fs or 384fs clocking. The datasheet explicitly defines this constraint in Section 7, confirming 55 kHz as the upper bound for 512fs operation.
Does UDA1345TS/N2,112 require an external crystal or oscillator?
No, the UDA1345TS/N2,112 does not include or require an internal or external crystal. It operates as a slave device, relying entirely on externally supplied SYSCLK, BCK, and WS signals from a host controller or audio processor. The datasheet states in Section 7 that "the system devices must provide the system clocks," with no provision for crystal connections or oscillator circuitry on the UDA1345TS/N2,112 die.
Can UDA1345TS/N2,112 drive headphones directly?
No, the UDA1345TS/N2,112 is specified for line-level output only (900 mVRMS into 5 kΩ), not headphone driving. Its VOUTL/VOUTR pins deliver sufficient voltage for line inputs but lack the current capability (<3 mA per channel) required for typical 16–32 Ω headphone loads. Driving headphones directly would result in severe distortion and insufficient volume-external headphone amplifiers are required.
What is the purpose of the Vref(D) pin (pin 28) on UDA1345TS/N2,112?
Vref(D) (pin 28) serves as the reference voltage input for the DAC section. Per Section 6 and Figure 1 of the datasheet, it sets the full-scale output range of the Filter Stream DAC-output voltage scales proportionally with Vref(D). It must be connected to a stable analog voltage (typically VDDA(DAC)/2) to ensure accurate DAC linearity and prevent gain drift across temperature and supply variations.
Is UDA1345TS/N2,112 pin-compatible with UDA1340M?
Yes, the UDA1345TS/N2,112 is pin- and function-compatible with the UDA1340M-but only when both devices operate in L3 microcontroller mode. Section 7.9 confirms this compatibility explicitly: "in L3MODE the UDA1345TS is completely pin and function compatible with the UDA1340M and the UDA1344TS." Static pin mode configurations differ, so interoperability is mode-dependent.
UDA1345TS/N2,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 28-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Stereo Audio
- Data Interface:
- Serial
- Resolution (Bits):
- 24 b
- Number of ADCs / DACs:
- 2 / 2
- Sigma Delta:
- Yes
- S/N Ratio, ADCs / DACs (db) Typ:
- 94 / 98
- Dynamic Range, ADCs / DACs (db) Typ:
- -
- Voltage - Supply, Analog:
- 2.4V ~ 3.6V
- Voltage - Supply, Digital:
- 2.4V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SSOP
UDA1345TS/N2,112 FAQ
1.How can I place an order for UDA1345TS/N2,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for UDA1345TS/N2,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UDA1345TS/N2,112 reliable?
The price and inventory of UDA1345TS/N2,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UDA1345TS/N2,112 is usually 5 days.
3.What payment methods are accepted for UDA1345TS/N2,112?
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UDA1345TS/N2,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UDA1345TS/N2,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UDA1345TS/N2,112?
For technical support, including UDA1345TS/N2,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UDA1345TS/N2,112 requirements.
6.How does Aetrix verify that UDA1345TS/N2,112 is sourced from the original manufacturer or authorized distributors?
All UDA1345TS/N2,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UDA1345TS/N2,112 meets industry standards.
7.What is the process for return or replacement of UDA1345TS/N2,112?
All UDA1345TS/N2,112 units undergo pre-shipment inspection (PSI). If there is an issue with UDA1345TS/N2,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UDA1345TS/N2,112 part is unused and in its original packaging.
Return procedure for UDA1345TS/N2,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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