NXP Semiconductors UDA1355H/N2,557

Overview

UDA1355H/N2,557 from NXP Semiconductors is a stereo audio codec IC integrating IEC 60958 SPDIF decoder/encoder, 24-bit ADC with PGA, and 24-bit DAC with interpolator and noise shaper. It operates from 2.7–3.6 V, supports 16–100 kHz sampling rates, and delivers −88 dB THD+N (48 kHz) and 98 dB SNR. It is used in digital audio receivers, set-top boxes, and AV receivers requiring SPDIF passthrough and analog/digital conversion.

For engineers reviewing the UDA1355H/N2,557 datasheet, UDA1355H/N2,557 pinout, UDA1355H/N2,557 application, or UDA1355H/N2,557 equivalent, key selection criteria include SPDIF input channel selection (4-channel), dual clock system (12.288 MHz crystal + PLL lock), microcontroller-configurable audio processing (L3/I²C), and support for 32/44.1/48/96 kHz de-emphasis and soft mute.

Technical Context

The UDA1355H/N2,557 implements a dual-clock architecture: one based on an external 12.288 MHz crystal oscillator driving the DAC, SPDIF encoder, and CLK_OUT (256fs/384fs), and another PLL-based system locking to incoming SPDIF or I2S signals for jitter-free ADC timing. Its bitstream conversion architecture uses a 64fs ADC decimator (comb + three half-band FIR filters) and a 64fs/128fs DAC interpolator (recursive + FIR) with selectable 3rd- or 5th-order noise shapers.

Control is implemented via static pins (limited mode) or full-feature L3-bus/I²C interfaces (up to 2 MHz / 400 kHz), enabling real-time configuration of PGA gain (0–24 dB), digital volume (−63.5 to +24 dB), bass/treble boost, channel status bits (40 per channel), and SPDIF source selection. The LOCK pin provides hardware PLL lock indication, and MUTE enables cosine-roll-off soft muting.

Key Specifications

Pinout & Package

UDA1355H/N2,557 is housed in a 44-pin plastic quad flat package (QFP44, SOT307-2), 10 × 10 × 1.75 mm body, 1.3 mm lead length.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar stereo audio codec applications.

Compared with AK4118VN and CS4272-CQZ, the UDA1355H/N2,557 uniquely integrates four SPDIF inputs, L3/I²C dual-control, on-chip PGA, and full SPDIF encode/decode-making it the only option among the three supporting true SPDIF loop-through with real-time channel status editing and analog front-end gain staging.

Availability

UDA1355H/N2,557 is available at Aetrix Electronics and suitable for digital audio receivers, AV receivers, and professional monitor interfaces requiring stable component supply, long-term lifecycle support, and consistent SPDIF timing compliance.

Supply support for UDA1355H/N2,557 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer electronics.

The UDA1355H/N2,557 belongs to NXP's legacy audio codec product line, designed specifically for high-fidelity digital audio systems requiring integrated SPDIF interface, flexible clocking, and software-configurable analog/digital signal processing.

FAQ

What is the required crystal frequency for UDA1355H/N2,557?

The UDA1355H/N2,557 requires a 12.288 MHz fundamental-mode crystal connected between XTALIN and XTALOUT pins. This frequency is mandatory for generating standard audio sampling rates (32/44.1/48 kHz and their multiples) and cannot be substituted with other frequencies without violating timing specifications. The crystal must have a 10 pF load capacitance as specified in the datasheet.

Does UDA1355H/N2,557 support I²C and L3-bus simultaneously?

No, the UDA1355H/N2,557 supports either I²C-bus or L3-bus control-not both simultaneously. Mode selection is determined by the voltage level on SEL_STATIC pin: MID level enables I²C mode, LOW level enables L3-bus mode. Both interfaces share identical register mapping and functional access, but physical pin assignments differ (MP1/MP2 serve as SCL/SDA in I²C mode, L3CLOCK/L3DATA in L3 mode).

How does the LOCK pin function on UDA1355H/N2,557?

The LOCK pin on UDA1355H/N2,557 is an open-drain output that goes high when the internal PLL achieves stable lock to an incoming SPDIF or digital audio (e.g., I2S) clock signal. It remains low during unlock, power-up, or signal loss. This signal is used to gate DAC output and digital interface output by default, preventing audible artifacts during synchronization transients.

Can UDA1355H/N2,557 perform SPDIF passthrough without digital processing?

Yes, UDA1355H/N2,557 supports hardware SPDIF passthrough in microcontroller modes 2 and 13, and static modes 0 and 2. In these configurations, the selected SPDIF input (SPDIF0–SPDIF3) is routed directly to SPDIFOUT with no modification to channel status bits or audio data-enabling transparent digital audio routing while maintaining lock detection and mute control.

What is the maximum supported sampling rate for ADC and DAC in UDA1355H/N2,557?

The UDA1355H/N2,557 supports ADC and DAC sampling rates from 16 kHz to 100 kHz. Its SPDIF interface handles input frequencies from 28 kHz to 96 kHz with lock detection, and its SPDIF encoder generates outputs at 32/44.1/48 kHz (static mode) or those frequencies plus half/double values (microcontroller mode). The 100 kHz upper limit applies to non-SPDIF digital I/O (e.g., I2S) operation.