NXP Semiconductors UJA1061TW/3V3/C/T,

Overview

UJA1061TW/3V3/C/T from NXP Semiconductors is a fault-tolerant CAN/LIN System Basis Chip (SBC) integrating ISO 11898-3 CAN transceiver, LIN 2.0 transceiver, 3.3 V microcontroller regulator, 5 V CAN regulator, enhanced window watchdog, and SPI interface - designed for automotive ECUs requiring fail-safe power management, communication, and system supervision in 14 V/42 V architectures.

For engineers reviewing the UJA1061TW/3V3/C/T datasheet, UJA1061TW/3V3/C/T pinout, UJA1061TW/3V3/C/T application, or UJA1061TW/3V3/C/T equivalent, key selection criteria include its 3.3 V V1 output, HTSSOP32 package with exposed die pad, fail-safe state machine behavior, ±60 V bus-pin short-circuit protection, and support for cyclic wake-up in Standby/Sleep modes without CAN/LIN bus activation.

Technical Context

The UJA1061TW/3V3/C/T implements a dedicated fail-safe state machine supervised by an on-chip oscillator-clocked watchdog, managing six operating modes (Start-up, Restart, Normal, Standby, Sleep, Flash) with deterministic transitions triggered by reset sources, watchdog timeouts, bus activity, or local wake-up events. Its CAN transceiver supports partial networking and ground shift detection; LIN transceiver ensures backward compatibility with LIN 1.3 and TJA1020.

Power architecture includes independent regulators: V1 = 3.3 V (±2 %, 150 mA), V2 = 5 V (±2 %, 50 mA), and V3 = unregulated 42 V output with cyclic mode synchronized to WAKE input. Fail-safe reporting uses 23-bit protected RAM and single-SPI-message status encoding for diagnostics including V1 undervoltage, CAN/LIN bus faults, TXD/RXD clamping, and overtemperature.

Key Specifications

Pinout & Package

UJA1061TW/3V3/C/T is housed in a 32-pin HTSSOP package (SOT549-1) with 6.1 mm × 11 mm body, 0.65 mm pitch, and exposed die pad for thermal dissipation and EMC optimization. The die pad is electrically isolated and may be connected to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar System Basis Chip applications.

Compared with TJA1021T/CM,118, UJA1061TW/3V3/C/T provides full CAN/LIN integration and autonomous fail-safe control; compared with UJA1075TK/3V3/C/V, it uses a lower-power LDO-based V1 regulator and targets standard under-dash automotive environments.

Availability

UJA1061TW/3V3/C/T is available at Aetrix Electronics and suitable for automotive Body Control Modules, Engine Control Units, Transmission Control Modules, and ADAS sensor hubs requiring stable component supply, long-term lifecycle support, and AEC-Q100 qualified system basis functionality.

Supply support for UJA1061TW/3V3/C/T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with leadership in CAN, LIN, and functional-safety ICs.

The UJA1061 product line delivers fail-safe System Basis Chips for automotive ECUs, combining power regulation, communication interfaces, and autonomous supervision to simplify ECU design and improve ASIL-ready system robustness.

FAQ

What is the primary function of the UJA1061TW/3V3/C/T in an automotive ECU?

The UJA1061TW/3V3/C/T serves as a fail-safe System Basis Chip that integrates a 3.3 V microcontroller regulator, ISO 11898-3 fault-tolerant CAN transceiver, LIN 2.0 transceiver, enhanced watchdog, SPI interface, and power management logic. It replaces discrete components in automotive ECUs to ensure deterministic start-up, robust communication, and autonomous fault response - all within a single HTSSOP32 package. Its core purpose is to guarantee safe, controlled system behavior under fault conditions while enabling features like cyclic wake-up and limp-home activation.

Does the UJA1061TW/3V3/C/T support both 14 V and 42 V battery architectures?

Yes, the UJA1061TW/3V3/C/T supports dual-supply operation: BAT14 (Pin 27) accepts 14 V for standard automotive systems, while BAT42 (Pin 32) accepts up to 42 V for mild-hybrid architectures. In 14 V-only designs, BAT42 is connected to BAT14. The device generates V1 = 3.3 V, V2 = 5 V, and V3 = unregulated 42 V output - with V3 configurable in continuous, off, or cyclic mode synchronized to the WAKE input. All bus pins (CANH, CANL, LIN) are rated for ±60 V short-circuit protection, and battery inputs comply with ISO 7637 transient immunity.

How does the watchdog in the UJA1061TW/3V3/C/T differ from standard window watchdogs?

The UJA1061TW/3V3/C/T watchdog uses a fail-safe coded access protocol clocked directly by an on-chip oscillator, supporting four distinct modes: Start-up (reset supervision), Window (Normal mode, 50–100 % trigger window), Time-out (Standby/Sleep mode), and Off (fail-safe shutdown). Unlike generic watchdogs, it enforces redundant bit coding for SPI accesses - only ten valid period codes and six valid mode codes are accepted. Illegal codes or missed triggers force immediate reset into Start-up or Fail-safe mode. This architecture prevents software lockup and blind spots in safety-critical supervision.

Can the UJA1061TW/3V3/C/T be used without a CAN controller in the microcontroller?

No - the UJA1061TW/3V3/C/T requires a microcontroller with an integrated CAN controller. It provides only the physical layer (CAN transceiver) and associated power/regulation; the CAN protocol stack, message filtering, and arbitration must be handled by the host MCU. The UJA1061TW/3V3/C/T connects via TXDC (transmit data input) and RXDC (receive data output) pins to the MCU's CAN controller peripheral. Similarly, LIN communication relies on the MCU's LIN controller driving TXDL and reading RXDL. The device does not include on-chip CAN/LIN protocol engines.

What is the role of the INH/LIMP pin on the UJA1061TW/3V3/C/T?

The INH/LIMP pin (Pin 17) is a BAT14-referenced push-pull output that serves dual functions: "Inhibit" during normal operation (e.g., disabling external DC-DC converters or high-side switches), and "Limp-home" during Fail-safe mode. When the UJA1061TW/3V3/C/T enters Fail-safe mode due to critical faults (e.g., V1 undervoltage, oscillator failure), INH/LIMP is driven LOW to activate safety-critical hardware such as warning lights, brake lamps, or mechanical failsafe actuators. Its default floating state avoids unintended activation during power-up or reset sequences.