NXP Semiconductors UJA1061TW/3V3/C/T/
- Part No.:
- UJA1061TW/3V3/C/T/
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1061TW/3V3/C/T/.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1061TW/3V3/C/T/ from NXP Semiconductors is a fault-tolerant CAN/LIN System Basis Chip (SBC) integrating ISO 11898-3 CAN transceiver, LIN 2.0 transceiver, 3.3 V microcontroller regulator (V1), 5 V CAN regulator (V2), enhanced window watchdog with on-chip oscillator, and SPI interface - all in a single HTSSOP32 package for automotive ECU power and communication management.
For engineers reviewing the UJA1061TW/3V3/C/T/ datasheet, UJA1061TW/3V3/C/T/ pinout, UJA1061TW/3V3/C/T/ application, or UJA1061TW/3V3/C/T/ equivalent, this device serves as a fail-safe system controller enabling defined microcontroller startup, autonomous diagnostics, limp-home activation, and cyclic wake-up in 14 V/42 V architectures - critical for body control modules, gateway ECUs, and battery management systems.
Technical Context
The UJA1061TW/3V3/C/T/ implements a state-machine-based fail-safe system controller supervised by an on-chip oscillator-clocked watchdog, managing six operating modes (Start-up, Restart, Normal, Standby, Sleep, Flash) with mode transitions governed by SPI commands, bus activity, or hardware events. It supports partial networking via CAN global wake-up and local wake-up sampling on WAKE pin.
Its dual-regulator architecture isolates V1 (3.3 V for MCU) from V2 (5 V for CAN transceiver), while BAT14/BAT42 dual-supply inputs enable compatibility with 14 V and 42 V automotive architectures. Fault detection includes V1 undervoltage, CAN/LIN bus shorts/opens, reset line clamping, SPI message errors, and overtemperature - all reported via 23-bit protected RAM and consolidated SPI status messages.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Standard | ISO 11898-3 compliant fault-tolerant transceiver; enables robust communication in noisy automotive environments with bus-float capability when powered off. |
| LIN Standard | LIN 2.0 and SAE J2602 compliant; backward compatible with LIN 1.3 and TJA1020 for legacy subsystem integration. |
| V1 Output | 3.3 V ±3 % regulated output; powers microcontroller core logic with dedicated undervoltage monitoring and clamped-reset detection. |
| V2 Output | 5 V ±5 % regulated output; supplies CAN transceiver independently of V1, improving EMC and fault isolation. |
| Watchdog Type | Programmable window & time-out watchdog with on-chip oscillator; prevents software lockup and enables cyclic wake-up without MCU intervention. |
| SPI Interface | Fail-safe coded 16-bit SPI; supports register access, mode control, and consolidated 23-bit diagnostic reporting in single-frame reads. |
| Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm thermal-enhanced package with exposed die pad for low thermal resistance in high-power automotive applications. |
Pinout & Package
HTSSOP32 package (SOT549-1) with 32 leads, 0.65 mm pitch, 6.1 mm body width, and exposed die pad for thermal dissipation and improved EMC performance when connected to PCB ground.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Microcontroller supply output | 3.3 V regulated output; monitored for undervoltage and clamping; controls RSTN assertion during faults. |
| V2 | CAN transceiver supply output | 5 V regulated output; independent of V1; improves CAN bus EMC and fault containment. |
| RSTN | Active-low reset output | Drives microcontroller reset; detects external clamping (HIGH/LOW) and asserts extended reset during start-up. |
| INTN | Active-low interrupt output | Open-drain, wire-ANDable interrupt signal; requires response within tRSTN(INT) to avoid forced reset. |
| EN | Enable output | Push-pull active-HIGH signal; goes LOW on every reset/watchdog overflow to control external peripherals. |
| INH/LIMP | Inhibit/limp-home output | BAT14-referenced push-pull output; floats by default; drives warning lights or safety relays in Fail-safe mode. |
| WAKE | Local wake-up input | BAT42-referenced input; supports continuous or cyclic sampling to initiate wake-up from Standby/Sleep modes. |
| CANH / CANL | CAN bus differential pair | Fault-tolerant physical layer interface; pins are floating when unpowered; support ±60 V short-circuit protection. |
| LIN | LIN bus line | Single-wire LIN physical interface; LOW-dominant signaling; compatible with LIN 1.3/2.0 transceivers. |
| TXDC / RXDC | CAN data interface | Digital-level inputs/outputs between MCU and CAN transceiver; isolated from bus-side faults. |
| TXDL / RXDL | LIN data interface | Digital-level inputs/outputs between MCU and LIN transceiver; supports dominant/recessive level translation. |
| SCK / SDO / SDI / SCS | SPI interface | Full-duplex SPI bus; SDO floats when SCS is HIGH; all accesses fail-safe coded for corruption immunity. |
| BAT14 / BAT42 | Power supply inputs | BAT14 accepts 14 V systems; BAT42 accepts 42 V systems; connected together for 14 V-only operation. |
| SYSINH | System inhibit output | BAT42-referenced output; controls external DC-DC converters or high-side switches in multi-rail systems. |
| V3 | Unregulated 42 V output | BAT42-derived output; configurable as continuous, off, or cyclic (synchronized with WAKE) for external wake-up switches. |
Key Features
| Feature | Design Value |
|---|---|
| Fail-safe state machine | Hardware-enforced six-mode operation (Start-up, Restart, Normal, Standby, Sleep, Flash) with deterministic transitions and reset-source tracking. |
| Autonomous diagnostics | Detects and reports 12+ fault types (V1 undervoltage, CAN/LIN shorts, reset clamping, SPI errors, overtemperature) in single SPI read. |
| Limp-home activation | INH/LIMP output asserts in Fail-safe mode to drive safety-critical hardware (e.g., warning lamps) without MCU involvement. |
| Partial networking | CAN global wake-up allows selective node activation without disturbing sleeping nodes - reducing overall network current. |
| Cyclic wake-up capability | Watchdog or WAKE pin triggers periodic wake-up from Standby/Sleep modes, enabling ultra-low-power sensor polling. |
| EMC-hardened design | ±8 kV HBM ESD, ±6 kV IEC 61000-4-2, ISO 7637 transient protection, and floating bus pins improve robustness in harsh automotive environments. |
Applications
| Body Control Module (BCM) | Gateway ECU |
|---|---|
Use Scenario: Centralized control of door locks, lighting, wipers, and HVAC in modern vehicles using distributed LIN slaves and CAN backbone connectivity. IC Role / Device Role / Timing Role: UJA1061TW/3V3/C/T/ acts as primary power manager and fail-safe supervisor - regulating V1/V2, enabling CAN/LIN gateways, and asserting INH/LIMP during faults to maintain basic lighting functions. Use Value: Enables safe degradation (e.g., hazard lights remain active) during MCU failure while supporting remote flash programming via CAN-bus for OTA updates. | Use Scenario: Aggregating signals between high-speed CAN FD domains (powertrain, ADAS) and low-speed LIN clusters (seats, mirrors, sensors) in vehicle domain controllers. IC Role / Device Role / Timing Role: UJA1061TW/3V3/C/T/ provides isolated CAN/LIN transceivers, dual regulators, and SPI-managed mode switching - allowing selective wake-up of subnetworks without full system boot. Use Value: Reduces gateway standby current via cyclic wake-up and partial networking, meeting OEM requirements for <100 µA sleep current in parked vehicle mode. |
| Battery Management System (BMS) | Seat Control Module |
Use Scenario: Monitoring cell voltage, temperature, and contactor status in 48 V mild-hybrid battery packs, communicating via CAN to vehicle controller and LIN to cabin sensors. IC Role / Device Role / Timing Role: UJA1061TW/3V3/C/T/ delivers stable 3.3 V power to BMS MCU, regulates CAN transceiver at 5 V, and reports overtemperature or bus faults via SPI before thermal shutdown. Use Value: Prevents false resets during load dump transients (ISO 7637-2 Pulse 5a) due to integrated BAT14/BAT42 protection and guarded V1 regulation. | Use Scenario: Controlling motorized seat position, heating elements, and memory functions using LIN-connected actuators and CAN-linked driver profiles. IC Role / Device Role / Timing Role: UJA1061TW/3V3/C/T/ supplies 3.3 V to seat MCU, manages LIN communication with slave nodes, and activates INH/LIMP to disable motors during collision detection. Use Value: Ensures fail-safe motor cutoff during crash events via hardware-driven INH/LIMP assertion - independent of MCU firmware state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fail-safe SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1021T/CM | LIN-only SBC with no CAN transceiver; 5 V VCC output only; no V3 output or SYSINH pin. | Restricted to LIN-subsystem ECUs without CAN connectivity; lacks 42 V support and fail-safe state machine depth. | Select when cost-sensitive LIN-node applications require basic power management without CAN integration. |
| UJA1076TW/3V3/C/T | Successor with enhanced CAN FD support, lower sleep current (20 µA vs. 40 µA), and updated watchdog security features. | Designed for next-gen 12 V/48 V architectures requiring higher bandwidth and stricter cybersecurity compliance. | Prefer for new designs targeting ASAM MCD-2 MC-compliant diagnostics and ISO 11898-1:2015 CAN FD interoperability. |
Compared with TJA1021T/CM, UJA1061TW/3V3/C/T/ adds fault-tolerant CAN, dual-supply flexibility, and deeper fail-safe supervision - making it suitable for gateway and safety-critical roles. Against UJA1076TW/3V3/C/T/, it offers proven field reliability and broader toolchain support but lacks CAN FD and advanced security boot features.
Availability
UJA1061TW/3V3/C/T/ is available at Aetrix Electronics and suitable for body control modules, gateway ECUs, battery management systems, and seat control modules requiring stable component supply across automotive production lifecycles.
Supply support for UJA1061TW/3V3/C/T/ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications - with deep expertise in automotive-grade mixed-signal ICs and functional safety certification.
The UJA1061TW/3V3/C/T/ belongs to NXP's System Basis Chip product line, engineered specifically for fail-safe power and communication management in automotive electronic control units operating across 14 V and 42 V battery architectures.
FAQ
What is the primary function of the UJA1061TW/3V3/C/T/ in an automotive ECU?
The UJA1061TW/3V3/C/T/ serves as a fail-safe System Basis Chip that integrates power regulation (3.3 V V1 for MCU, 5 V V2 for CAN), fault-tolerant CAN and LIN transceivers, an enhanced window watchdog, SPI interface, and autonomous diagnostics. It ensures defined microcontroller startup, monitors system health, and activates limp-home outputs during faults - all critical for automotive ASIL-B compliant ECUs.
Does the UJA1061TW/3V3/C/T/ support both 14 V and 42 V automotive battery systems?
Yes, the UJA1061TW/3V3/C/T/ supports dual-supply architectures via separate BAT14 (14 V input) and BAT42 (42 V input) pins. In 14 V systems, BAT42 is connected to BAT14; in 42 V systems, BAT42 operates independently. The device regulates V1 and V2 from either supply, and V3 provides unregulated 42 V output for external wake-up switches - enabling use in conventional and mild-hybrid vehicles.
How does the UJA1061TW/3V3/C/T/ handle fault conditions like CAN bus short circuits?
The UJA1061TW/3V3/C/T/ detects CAN bus shorts and open-circuits through internal monitoring of CANH/CANL differential voltage and TXDC/RXDC clamping states. Upon detection, it reports the fault via SPI status registers, may assert RSTN to reset the MCU, and can transition to Fail-safe mode where INH/LIMP activates safety hardware. Bus pins are rated ±60 V short-circuit proof and protected per ISO 7637 against transients.
Can the UJA1061TW/3V3/C/T/ be used for remote firmware updates over CAN?
Yes, the UJA1061TW/3V3/C/T/ supports remote flash programming via the CAN-bus by enabling cyclic wake-up and partial networking - allowing targeted node activation without waking the entire network. Its fail-safe coded SPI interface and Flash mode entry sequence (111-001-111) ensure secure, corruption-resistant firmware loading while maintaining diagnostic visibility throughout the update process.
What is the role of the INH/LIMP pin on the UJA1061TW/3V3/C/T/?
The INH/LIMP pin on the UJA1061TW/3V3/C/T/ is a BAT14-referenced push-pull output that defaults to floating. In Fail-safe mode, it actively drives LOW or HIGH to activate safety-critical hardware - such as warning lights, hazard indicators, or relay cutoffs - independent of MCU firmware state. This hardware-enforced behavior ensures predictable system degradation during catastrophic failures.
UJA1061TW/3V3/C/T/ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Networking
- Interface:
- CAN, LIN
- Voltage - Supply:
- 5.5V ~ 27V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1061TW/3V3/C/T/ FAQ
1.How can I place an order for UJA1061TW/3V3/C/T/ through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1061TW/3V3/C/T/ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1061TW/3V3/C/T/ reliable?
The price and inventory of UJA1061TW/3V3/C/T/ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1061TW/3V3/C/T/ is usually 5 days.
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Once your UJA1061TW/3V3/C/T/ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1061TW/3V3/C/T/?
For technical support, including UJA1061TW/3V3/C/T/ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1061TW/3V3/C/T/ requirements.
6.How does Aetrix verify that UJA1061TW/3V3/C/T/ is sourced from the original manufacturer or authorized distributors?
All UJA1061TW/3V3/C/T/ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1061TW/3V3/C/T/ meets industry standards.
7.What is the process for return or replacement of UJA1061TW/3V3/C/T/?
All UJA1061TW/3V3/C/T/ units undergo pre-shipment inspection (PSI). If there is an issue with UJA1061TW/3V3/C/T/, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1061TW/3V3/C/T/ part is unused and in its original packaging.
Return procedure for UJA1061TW/3V3/C/T/:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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