NXP Semiconductors UJA1061TW/5V0/C/T/
- Part No.:
- UJA1061TW/5V0/C/T/
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1061TW/5V0/C/T/.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1061TW/5V0/C/T/ from NXP Semiconductors is a fault-tolerant CAN/LIN System Basis Chip (SBC) designed for automotive ECUs. It integrates an ISO 11898-3 compliant CAN transceiver, LIN 2.0 transceiver, 5.0 V microcontroller regulator (V1), 5 V CAN transceiver regulator (V2), and an enhanced window watchdog with on-chip oscillator. It enables fail-safe system startup, limp-home operation, and remote flash programming in 14 V and 42 V battery architectures.
For engineers reviewing the UJA1061TW/5V0/C/T/ datasheet, UJA1061TW/5V0/C/T/ pinout, UJA1061TW/5V0/C/T/ application, or UJA1061TW/5V0/C/T/ equivalent, key selection criteria include its dual-supply support (BAT14/BAT42), fail-safe state machine behavior, SPI-coded watchdog supervision, 32-pin HTSSOP package with exposed die pad, and integrated diagnostics reporting across CAN/LIN bus faults, voltage undervoltages, and thermal warnings.
Technical Context
The UJA1061TW/5V0/C/T/ implements a dedicated fail-safe state machine supervised by an on-chip oscillator-clocked watchdog, managing six defined operating modes (Start-up, Restart, Normal, Standby, Sleep, Flash) with deterministic transitions triggered by reset events, wake-up sources, or SPI commands. Its power architecture includes independent regulators: V1 (5.0 V ±2% for MCU), V2 (5 V for CAN transceiver), and V3 (unregulated 42 V output).
It supports partial networking via CAN global wake-up and cyclic local wake-up sampling on WAKE pin, while LIN and CAN transceivers provide error signaling per ISO 11898-3 and SAE J2602. Bus pins are short-circuit proof (±60 V), ESD protected (±8 kV HBM), and transient-hardened per ISO 7637.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Compliance | ISO 11898-3 fault-tolerant; enables robust communication in 12 V/24 V/42 V automotive networks with bus-float capability when powered off |
| LIN Compliance | LIN 2.0 and SAE J2602; backward compatible with LIN 1.3 and TJA1020 for legacy node integration |
| V1 Output | 5.0 V ±2% regulated output; powers external microcontroller with programmable reset lengthening and clamping detection on RSTN |
| V2 Output | 5 V regulator dedicated to CAN transceiver; isolated from V1 supply and guarded by CAN-bus failure management |
| Watchdog Mode | Programmable window or time-out mode; coded SPI access prevents accidental service; detects early/late triggers in Normal mode |
| Operating Temp | −40 °C to +150 °C junction temperature; qualified for under-hood automotive environments with overtemperature warning reporting |
| Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm body, 0.65 mm pitch, exposed die pad for thermal dissipation and EMC grounding |
Pinout & Package
UJA1061TW/5V0/C/T/ uses a 32-pin HTSSOP package (SOT549-1) with 0.65 mm lead pitch and exposed die pad for thermal and EMC performance. The die pad is electrically isolated and may be connected to GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 (Pin 4) | Microcontroller supply output | 5.0 V regulated output; monitors undervoltage and clamping; drives RSTN during faults |
| V2 (Pin 20) | CAN transceiver supply output | 5 V regulator independent of V1; enables CAN operation during MCU brownout |
| RSTN (Pin 6) | Reset output to MCU | Active-low open-drain reset with clamping detection; held LOW during Start-up and Fail-safe modes |
| INTN (Pin 7) | Interrupt output to MCU | Active-low open-drain interrupt; wire-AND capable; requires response within tRSTN(INT) to avoid reset |
| INH/LIMP (Pin 17) | Inhibit/limp-home output | BAT14-referenced push-pull output; floats by default; asserts LOW in Fail-safe mode to activate warning hardware |
| WAKE (Pin 18) | Local wake-up input | BAT42-referenced input; supports continuous or cyclic sampling for low-power wake-up without bus activity |
| CANH/CANL (Pins 21/22) | CAN bus interface | Fault-tolerant differential pair; ±60 V short-circuit rated; floating when unpowered; supports ground shift detection |
| LIN (Pin 25) | LIN bus line | Single-wire bus interface; dominant LOW; supports LIN 2.0 framing and slave node diagnostics |
Key Features
| Feature | Design Value |
|---|---|
| Fail-safe state machine | Deterministic six-mode operation (Start-up, Normal, Standby, Sleep, Fail-safe, Flash) with automatic recovery paths and reset-source reporting |
| SPI-coded watchdog | Redundant-bit SPI access ensures fail-safe supervision; illegal codes force immediate reset; window mode enforces software timing discipline |
| Integrated diagnostics | Single-SPI-message reporting of 23 fault categories including CAN/LIN bus shorts/opens, V1 undervoltage, oscillator failure, and overtemperature |
| Partial networking | Global wake-up via CAN allows selective node activation without waking entire network; reduces system quiescent current |
| 42 V BAT-compatible output | V3 pin delivers unregulated 42 V output in continuous or cyclic mode; drives external wake-up switches or relays directly |
Applications
| Body Control Module (BCM) | Engine Control Unit (ECU) |
|---|---|
Use Scenario: Centralized vehicle lighting, door lock, and window control with LIN-connected sensors and actuators. IC Role / Device Role / Timing Role: UJA1061TW/5V0/C/T/ serves as primary power manager and communication hub, regulating MCU voltage (V1), powering CAN gateway, and enabling limp-home activation via INH/LIMP during fault. Use Value: Enables safe degradation (e.g., flashing hazard lights) during MCU or bus failure, supported by detailed diagnostics reported over SPI. | Use Scenario: Real-time engine monitoring and actuation using CAN for sensor fusion and LIN for throttle/valve position feedback. IC Role / Device Role / Timing Role: UJA1061TW/5V0/C/T/ provides fail-safe startup sequence, autonomous watchdog supervision, and isolated V2 supply to ensure CAN transceiver remains operational during V1 brownout. Use Value: Guarantees deterministic reset behavior and sustained CAN communication even during transient battery dips, critical for emission compliance. |
| Transmission Control Module (TCM) | Advanced Driver Assistance Systems (ADAS) ECU |
Use Scenario: Gearshift logic and hydraulic pressure control with CAN-based torque requests and LIN-connected solenoid drivers. IC Role / Device Role / Timing Role: UJA1061TW/5V0/C/T/ manages power sequencing, detects CANH/CANL shorts via RTL/RTH pins, and asserts limp-home signal to hold gear in safe position. Use Value: Prevents undefined transmission states during bus faults by triggering controlled fallback via INH/LIMP and reporting root cause in single SPI frame. | Use Scenario: Sensor fusion ECU aggregating radar, camera, and ultrasonic data with CAN backbone and LIN-connected proximity sensors. IC Role / Device Role / Timing Role: UJA1061TW/5V0/C/T/ supplies stable V1/V2, enables remote flash programming over CAN, and monitors thermal faults via on-die sensor with overtemperature warning. Use Value: Supports ASIL-B–aligned safety mechanisms through autonomous fail-safe behavior and diagnostic coverage of power, bus, and thermal domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar System Basis Chip applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1021T/CM | LIN-only SBC; no CAN transceiver; 3.3 V V1 output; lacks V3 42 V output and fail-safe state machine complexity | Suitable for LIN-slave nodes only; cannot replace UJA1061TW/5V0/C/T/ in CAN gateway or dual-bus ECUs | Select only for cost-sensitive LIN-peripheral modules where CAN integration and fail-safe supervision are unnecessary |
| UJA1075TK/3V3/C/T | 3.3 V V1 version; identical pinout and feature set; shares same HTSSOP32 package and SPI register map | Direct drop-in replacement where MCU requires 3.3 V supply instead of 5.0 V; all other functionality preserved | Choose when interfacing with 3.3 V microcontrollers; verify V1 load current and thermal derating match design requirements |
Compared with TJA1021T/CM and UJA1075TK/3V3/C/T, the UJA1061TW/5V0/C/T/ uniquely combines fault-tolerant CAN, LIN, dual-regulator power management, and a full fail-safe state machine in one HTSSOP32 device-making it irreplaceable in safety-critical dual-bus automotive ECUs requiring limp-home capability and comprehensive diagnostics.
Availability
UJA1061TW/5V0/C/T/ is available at Aetrix Electronics and suitable for Body Control Modules, Engine Control Units, Transmission Control Modules, and ADAS ECUs requiring stable component supply, automotive-grade reliability, and long-term lifecycle continuity.
Supply support for UJA1061TW/5V0/C/T/ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The UJA1061 product line delivers fail-safe System Basis Chips for automotive ECUs, integrating power regulation, CAN/LIN transceivers, watchdog supervision, and diagnostics to simplify ECU design and enhance functional safety compliance.
FAQ
What is the function of the INH/LIMP pin on the UJA1061TW/5V0/C/T/?
The INH/LIMP pin (Pin 17) is a BAT14-referenced push-pull output that defaults to floating. In Fail-safe mode, it asserts LOW to activate external warning hardware such as hazard lights or dashboard indicators. During Normal mode, it can be driven HIGH or LOW via SPI to control external loads like relays or DC-DC enable lines. Its behavior is fully programmable and synchronized with the SBC's state machine transitions.
Does the UJA1061TW/5V0/C/T/ support remote firmware updates over CAN?
Yes, the UJA1061TW/5V0/C/T/ supports remote flash programming via the CAN bus. It enters Flash mode only after a secure three-step SPI handshake (111 → 001 → 111) followed by Operating Mode code 011. This fail-safe entry sequence prevents accidental activation and ensures the microcontroller validates the update path before reprogramming begins.
What are the key differences between the UJA1061TW/5V0/C/T/ and UJA1075TK/3V3/C/T/?
The UJA1061TW/5V0/C/T/ and UJA1075TK/3V3/C/T/ share identical pinout, HTSSOP32 package, SPI register map, and fail-safe state machine. Their sole difference is V1 output voltage: 5.0 V ±2% for UJA1061TW/5V0/C/T/ versus 3.3 V ±2% for UJA1075TK/3V3/C/T/. All other features-including CAN/LIN transceivers, watchdog, diagnostics, and V2/V3 outputs-are functionally identical.
How does the UJA1061TW/5V0/C/T/ handle CAN bus faults such as short circuits?
The UJA1061TW/5V0/C/T/ detects CANH/CANL short-to-battery, short-to-ground, and open-wire faults using internal comparators and reports them via dedicated status bits in the SPI Fault Register. It also provides RTL and RTH pins to connect external termination resistors, enabling configurable bus termination during fault conditions to maintain partial network operation.
What is the purpose of the V3 pin on the UJA1061TW/5V0/C/T/?
The V3 pin delivers an unregulated 42 V output referenced to BAT42. It operates in continuous, off, or cyclic mode synchronized with the local wake-up input (WAKE). This output drives high-side external loads such as wake-up switches, relays, or solenoids without requiring additional DC-DC stages-reducing BOM count and improving system-level efficiency in 42 V architectures.
UJA1061TW/5V0/C/T/ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Networking
- Interface:
- CAN, LIN
- Voltage - Supply:
- 5.5V ~ 27V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1061TW/5V0/C/T/ FAQ
1.How can I place an order for UJA1061TW/5V0/C/T/ through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1061TW/5V0/C/T/ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1061TW/5V0/C/T/ reliable?
The price and inventory of UJA1061TW/5V0/C/T/ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1061TW/5V0/C/T/ is usually 5 days.
3.What payment methods are accepted for UJA1061TW/5V0/C/T/?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1061TW/5V0/C/T/ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1061TW/5V0/C/T/?
UJA1061TW/5V0/C/T/ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1061TW/5V0/C/T/ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1061TW/5V0/C/T/?
For technical support, including UJA1061TW/5V0/C/T/ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1061TW/5V0/C/T/ requirements.
6.How does Aetrix verify that UJA1061TW/5V0/C/T/ is sourced from the original manufacturer or authorized distributors?
All UJA1061TW/5V0/C/T/ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1061TW/5V0/C/T/ meets industry standards.
7.What is the process for return or replacement of UJA1061TW/5V0/C/T/?
All UJA1061TW/5V0/C/T/ units undergo pre-shipment inspection (PSI). If there is an issue with UJA1061TW/5V0/C/T/, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1061TW/5V0/C/T/ part is unused and in its original packaging.
Return procedure for UJA1061TW/5V0/C/T/:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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