NXP Semiconductors UJA1065TW/5V0,512
- Part No.:
- UJA1065TW/5V0,512
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1065TW/5V0,512.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1065TW/5V0 from NXP Semiconductors is a fail-safe System Basis Chip (SBC) integrating high-speed CAN and LIN transceivers, dual voltage regulators (5.0 V for MCU and 5 V for CAN), an enhanced window watchdog with on-chip oscillator, SPI interface, and limp-home output. It serves as the central power, communication, and safety supervisor in automotive ECUs requiring ISO 11898-2/5 and LIN 2.0 compliance.
For engineers reviewing the UJA1065TW/5V0 datasheet, UJA1065TW/5V0 pinout, UJA1065TW/5V0 application, or UJA1065TW/5V0 equivalent, key selection criteria include its 5.0 V microcontroller regulator output, HTSSOP32 package with exposed die pad, fail-safe state machine behavior, partial networking support, and 42 V battery-compatible architecture.
Technical Context
The UJA1065TW/5V0 implements a dedicated fail-safe state machine supervised by an on-chip oscillator-clocked watchdog, managing seven distinct operating modes (Start-up, Restart, Normal, Standby, Sleep, Flash, Fail-safe) with deterministic transitions. Its CAN transceiver supports ISO 11898-2/5, includes SPLIT output for recessive bus stabilization, and features partial networking with global wake-up capability.
The LIN transceiver complies with LIN 2.0 and SAE J2602, is downward compatible with LIN 1.3 and TJA1020, and shares the same fail-safe supervision logic. Power management includes cyclic wake-up in Standby/Sleep modes, BAT42-related V3 output (cyclic or continuous), and system inhibit (SYSINH) control of external DC-DC converters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Standard | ISO 11898-2 and ISO 11898-5 compliant; enables interoperability with TJA1041/TJA1041A and robust EMC performance |
| LIN Standard | LIN 2.0 and SAE J2602 compliant; backward compatible with LIN 1.3 and TJA1020 for legacy integration |
| V1 Output | 5.0 V regulated output for microcontroller; fixed version denoted by /5V0 suffix; supports defined startup and undervoltage detection |
| V2 Output | 5 V regulator for CAN transceiver; independent from V1 supply and guarded by CAN-bus failure management |
| Watchdog Mode | Programmable window mode (Normal mode) and time-out mode (Standby/Sleep/Flash); coded SPI access prevents accidental resets |
| Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm body, 0.65 mm pitch, exposed die pad for thermal dissipation and EMC optimization |
| ESD Protection | ±8 kV HBM and ±4 kV IEC 61000-4-2 on off-board pins; ensures robustness in automotive assembly and field environments |
Pinout & Package
UJA1065TW/5V0 uses the HTSSOP32 (SOT549-1) package: plastic thermal-enhanced thin shrink small outline, 32 leads, 6.1 mm body width, 0.65 mm lead pitch, and exposed die pad for improved thermal conduction and EMC performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Microcontroller regulator output | 5.0 V supply for MCU; monitored for undervoltage; controls reset timing and fail-safe entry |
| V2 | CAN transceiver regulator output | 5 V supply for internal CAN transceiver; isolated from V1 to prevent coupling faults |
| RSTN | Reset output | Active-low open-drain reset signal to MCU; detects clamping and provides reset lengthening in Start-up mode |
| INTN | Interrupt output | Active-low open-drain interrupt to MCU; wire-AND capable; requires read within tRSTN(INT) to avoid forced reset |
| INH/LIMP | Inhibit/limp-home output | BAT14-related push-pull output; floats by default; drives warning lights or safety hardware in Fail-safe mode |
| SCK/SDI/SDO/SCS | SPI interface | Full-duplex SPI (clock, data in, data out, chip select); fail-safe coded protocol prevents misconfiguration |
| CANH/CANL | CAN bus interface | Differential high-speed CAN physical layer; ±60 V short-circuit proof; floating when unpowered |
| LIN/RTLIN | LIN bus interface | LIN 2.0 physical layer with termination resistor connection; supports local wake-up and diagnostics |
| WAKE | Local wake-up input | BAT42-related input; supports continuous or cyclic sampling for low-power ECU wake-up |
| BAT14/BAT42 | Power inputs | 14 V and 42 V battery supply inputs; connected together in 14 V systems; enable dual-voltage architecture support |
| SYSINH | System inhibit output | BAT42-related output; controls external DC-DC converter; maintains V2 during low-power states |
| V3 | Unregulated 42 V output | BAT42-related output; configurable as continuous, OFF, or cyclic (synchronized with WAKE) for external wake-up switches |
Key Features
| Feature | Design Value |
|---|---|
| Fail-safe state machine | Seven deterministic operating modes with autonomous transitions; prevents deadlock and guarantees controlled behavior under all fault conditions |
| Partial networking | Global wake-up capability allows selective CAN communication without waking sleeping nodes; reduces system power consumption |
| Fail-safe SPI interface | Coded 16-bit SPI protocol prevents accidental register writes; enables secure flash programming and diagnostics |
| 23-bit protected RAM | Access-protected memory for logging cyclic issues or diagnostic data; supports root-cause analysis without external storage |
| Comprehensive failure reporting | Single-SPI-message status reporting covering oscillator failure, bus shorts/opens, TXD/RXD clamping, overtemperature, and ground shift |
| Limp-home activation | Dedicated INH/LIMP output activates safety hardware (e.g., warning lights) upon Fail-safe mode entry; ensures driver awareness |
Applications
| Body Control Module (BCM) | Engine Control Unit (ECU) |
|---|---|
Use Scenario: Centralized vehicle body functions including door locks, lighting, and window control managed via CAN and LIN networks. IC Role / Device Role / Timing Role: UJA1065TW/5V0 acts as the primary power, communication, and fail-safe supervisor-providing regulated 5.0 V for MCU, CAN/LIN physical layers, and autonomous watchdog supervision. Use Value: Enables reliable low-power sleep/wake cycles with local and bus-triggered wake-up, reducing quiescent current to <100 µA while maintaining diagnostic readiness. | Use Scenario: Real-time engine management system requiring robust CAN communication, precise reset timing, and fault-tolerant operation under harsh thermal and electrical conditions. IC Role / Device Role / Timing Role: UJA1065TW/5V0 supplies critical 5.0 V power to the engine MCU, monitors V1 undervoltage, and delivers fail-safe reset/interrupt signaling synchronized with CAN bus activity. Use Value: Prevents undefined MCU behavior during battery transients (ISO 7637-3 compliant) and ensures safe shutdown via limp-home output when critical faults occur. |
| Advanced Driver Assistance Systems (ADAS) Sensor Hub | Electric Power Steering (EPS) Module |
Use Scenario: Aggregation and preprocessing of radar, camera, and ultrasonic sensor data using LIN-connected peripherals and CAN backhaul to central ADAS domain controller. IC Role / Device Role / Timing Role: UJA1065TW/5V0 provides isolated 5 V power to sensor interface MCU, LIN transceiver for peripheral communication, and fail-safe watchdog supervision with detailed bus failure reporting. Use Value: Detects and reports LIN bus opens/shorts and CAN dominant timeouts in real time, enabling rapid sensor fault isolation without host MCU intervention. | Use Scenario: Safety-critical steering assist system requiring ASIL-B capable power management, redundant communication paths, and guaranteed reset behavior during voltage sags. IC Role / Device Role / Timing Role: UJA1065TW/5V0 delivers 5.0 V MCU supply with undervoltage lockout, monitors CAN/LIN bus integrity, and asserts limp-home output to activate mechanical fallback steering indicators. Use Value: Supports cyclic wake-up from Sleep mode via watchdog or CAN activity, enabling fast reactivation (<100 ms) after torque demand events while maintaining functional safety. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fail-safe SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1021T/CM,118 | LIN-only SBC with 5 V regulator; lacks CAN transceiver, watchdog window mode, and 42 V support | Suitable for LIN-centric modules without CAN requirements; lower integration and cost | Select when only LIN interface and basic power management are needed; not suitable for CAN-based ECUs |
| UJA1075TK/5V0,518 | Successor SBC with enhanced CAN FD support, extended temperature range (−40 °C to +150 °C), and updated SPI security features | Designed for next-gen automotive platforms requiring higher bandwidth and extended reliability | Choose for new designs targeting CAN FD, higher ambient temperatures, or updated functional safety requirements |
Compared with TJA1021T/CM,118 and UJA1075TK/5V0,518, the UJA1065TW/5V0 offers balanced integration of high-speed CAN, LIN, and fail-safe supervision in a mature, widely deployed automotive SBC-ideal for cost-sensitive 14 V/42 V ECUs where CAN FD is not required.
Availability
UJA1065TW/5V0 is available at Aetrix Electronics and suitable for automotive body control, engine management, ADAS sensor hubs, and electric power steering systems requiring stable component supply across long production lifecycles.
Supply support for UJA1065TW/5V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, IoT, and communication infrastructure solutions, with deep expertise in automotive-grade mixed-signal ICs and functional safety.
The UJA1065TW/5V0 belongs to NXP's System Basis Chip product line, designed specifically to consolidate power, communication, and fail-safe supervision functions into a single IC for automotive electronic control units operating in 14 V and 42 V battery architectures.
FAQ
What is the function of the SPLIT pin on the UJA1065TW/5V0?
The SPLIT pin on the UJA1065TW/5V0 stabilizes the recessive common-mode voltage level on the CAN bus by connecting to a split termination network (typically two 60 Ω resistors to Vref). This improves signal integrity and EMC performance in high-noise automotive environments. It is directly tied to the internal CAN transceiver's differential receiver and must be used with external passive components per the layout guidelines in the UJA1065TW/5V0 datasheet.
Does the UJA1065TW/5V0 support both 14 V and 42 V battery systems simultaneously?
Yes, the UJA1065TW/5V0 supports dual-voltage architectures: BAT14 accepts 14 V supply and BAT42 accepts up to 42 V. In 14 V systems, BAT42 is connected to BAT14; in 42 V systems, they operate independently. The V3 output is BAT42-related and configurable for cyclic or continuous operation, enabling compatibility with both legacy and next-generation vehicle electrical architectures without redesign.
How does the UJA1065TW/5V0 handle watchdog service in Flash mode?
In Flash mode, the UJA1065TW/5V0 requires watchdog service using Operating Mode code 111 via SPI-distinct from Normal mode's window codes. Failure to use this exact code, or watchdog timeout, forces immediate reset to Start-up mode. This coded requirement prevents accidental exit from Flash mode during firmware updates and ensures secure, fail-safe programming sequences for automotive ECUs.
What is the purpose of the INH/LIMP pin on the UJA1065TW/5V0?
INH/LIMP is a BAT14-related push-pull output on the UJA1065TW/5V0 that defaults to floating. In Fail-safe mode, it drives HIGH or LOW to activate hardware such as warning lights or mechanical fallback indicators. During normal operation, it can be used as an inhibit signal to disable external loads (e.g., relays). Its behavior is programmable via SPI and tightly coupled to the SBC's fail-safe state machine.
Can the UJA1065TW/5V0 be used with a 3.3 V microcontroller?
No-the UJA1065TW/5V0 variant with /5V0 suffix provides a fixed 5.0 V V1 output and is not compatible with 3.3 V microcontrollers. For 3.3 V MCU support, the UJA1065TW/3V3 variant must be used. Both share identical pinout and functionality except for the V1 regulator voltage; substituting /5V0 for /3V3 risks overvoltage damage to the MCU and invalidates the power sequencing design.
UJA1065TW/5V0,512 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Networking
- Interface:
- SPI Serial
- Voltage - Supply:
- 5.5V ~ 52V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1065TW/5V0,512 FAQ
1.How can I place an order for UJA1065TW/5V0,512 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1065TW/5V0,512 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1065TW/5V0,512 reliable?
The price and inventory of UJA1065TW/5V0,512 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1065TW/5V0,512 is usually 5 days.
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UJA1065TW/5V0,512 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1065TW/5V0,512 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1065TW/5V0,512?
For technical support, including UJA1065TW/5V0,512 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1065TW/5V0,512 requirements.
6.How does Aetrix verify that UJA1065TW/5V0,512 is sourced from the original manufacturer or authorized distributors?
All UJA1065TW/5V0,512 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1065TW/5V0,512 meets industry standards.
7.What is the process for return or replacement of UJA1065TW/5V0,512?
All UJA1065TW/5V0,512 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1065TW/5V0,512, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1065TW/5V0,512 part is unused and in its original packaging.
Return procedure for UJA1065TW/5V0,512:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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