NXP Semiconductors UJA1065TW/5V0/C/T,
- Part No.:
- UJA1065TW/5V0/C/T,
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1065TW/5V0/C/T,.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1065TW/5V0/C/T from NXP Semiconductors is a fail-safe System Basis Chip (SBC) integrating high-speed CAN and LIN transceivers, dual voltage regulators (5 V for MCU, 5 V for CAN), an enhanced window watchdog with on-chip oscillator, SPI interface, and limp-home output. It serves as the central power, communication, and safety supervisor in automotive ECUs requiring ISO 11898-2/5 and LIN 2.0 compliance, 14 V/42 V dual-supply support, and fail-safe system startup.
For engineers reviewing the UJA1065TW/5V0/C/T datasheet, UJA1065TW/5V0/C/T pinout, UJA1065TW/5V0/C/T application, or UJA1065TW/5V0/C/T equivalent, key selection criteria include its 32-pin HTSSOP package, 5 V microcontroller regulator output, fail-safe coded SPI interface, partial networking capability, and ±60 V short-circuit protected CAN/LIN bus pins.
Technical Context
The UJA1065TW/5V0/C/T implements a state-machine-based fail-safe system controller supervised by an on-chip oscillator-clocked watchdog, supporting six distinct operating modes (Start-up, Restart, Normal, Standby, Sleep, Flash) with programmable transitions via SPI. Its CAN transceiver includes SPLIT output for recessive bus stabilization and partial networking with global wake-up, while the LIN transceiver supports LIN 2.0, SAE J2602, and backward compatibility with LIN 1.3.
Power management integrates independent low-dropout regulators (V1 = 5 V, V2 = 5 V), a 42 V high-side switch (V3), BAT14/BAT42 dual-input architecture, and cyclic wake-up capability in Standby/Sleep modes. Fail-safe reporting covers 23 bits of access-protected RAM for diagnostics, single-SPI-message status readout, and detection of oscillator failure, bus shorts/opens, clamped reset, overtemperature, and ground shift.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Standard | ISO 11898-2 and ISO 11898-5 compliant; enables interoperability with TJA1041/TJA1041A and robust EMC performance |
| LIN Standard | LIN 2.0 and SAE J2602 compliant; downward compatible with LIN 1.3 and TJA1020 for legacy integration |
| V1 Output | 5.0 V regulated output for microcontroller; fixed version per part number UJA1065TW/5V0 |
| V2 Output | 5 V dedicated regulator for CAN transceiver; independent from V1 supply and guarded by CAN-bus failure management |
| Watchdog Type | Programmable fail-safe coded window and time-out watchdog with on-chip oscillator; prevents blind spots during software execution |
| Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm body, 0.65 mm pitch, exposed die pad for thermal dissipation and EMC optimization |
| ESD Protection | ±8 kV HBM and ±4 kV IEC 61000-4-2 on off-board pins; ensures robustness in automotive assembly and field environments |
| Bus Fault Tolerance | ±60 V short-circuit proof CAN/LIN bus pins; eliminates need for external transient protection in most ECU designs |
Pinout & Package
UJA1065TW/5V0/C/T uses the HTSSOP32 (SOT549-1) package: plastic thermal enhanced thin shrink small outline package with 32 leads, 6.1 mm body width, 0.65 mm lead pitch, and exposed die pad for improved thermal resistance and EMC performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Microcontroller supply output | 5.0 V regulated output; powers host MCU and defines system logic level reference |
| V2 | CAN transceiver supply output | 5 V dedicated LDO; isolated from V1 to prevent CAN faults from disrupting MCU operation |
| RSTN | Reset output to MCU | Active-low open-drain reset; detects clamping situations and asserts during all fail-safe transitions |
| INTN | Interrupt output to MCU | Active-low open-drain interrupt; wire-AND capable for multi-interrupt ECU architectures |
| INH/LIMP | Inhibit/limp-home output | BAT14-referenced push-pull output; floats by default, drives warning lights or safety hardware in Fail-safe mode |
| SCK/SDI/SDO/SCS | SPI interface | Full-duplex SPI with fail-safe coded protocol; enables secure register access and diagnostics reporting |
| TXDC/RXDC | CAN data interface | CMOS-level inputs/outputs for MCU-side CAN controller; supports dominant/recessive signaling per ISO 11898 |
| CANH/CANL/SPLIT | CAN bus interface | Differential bus lines with SPLIT output for common-mode stabilization; floating when unpowered |
| TXDL/RXDL/LIN/RTLIN | LIN bus interface | Single-wire LIN transceiver with termination control; compliant with LIN 2.0 bus electrical requirements |
| WAKE | Local wake-up input | BAT42-referenced input; supports continuous or cyclic sampling for low-power ECU wake-up |
| BAT14/BAT42 | Power supply inputs | Dual battery inputs for 14 V and 42 V architectures; BAT42 connects to BAT14 in 14 V systems |
| V3 | 42 V switched output | BAT42-referenced high-side switch; delivers continuous or cyclic output for relays or wake-up switches |
Key Features
| Feature | Design Value |
|---|---|
| Fail-safe coded SPI interface | Enables tamper-resistant register access and diagnostics reporting without assembling multiple SPI frames |
| Partial networking with global wake-up | Allows selective CAN communication without waking sleeping nodes, reducing overall ECU current consumption |
| 23-bit access-protected RAM | Stores cyclic diagnostic logs (e.g., bus errors, voltage faults) for post-failure analysis without external memory |
| Programmable watchdog window mode | Detects both too-early and too-late MCU service calls in Normal mode, ensuring strict timing supervision |
| Limp-home output activation | Drives safety-critical hardware (e.g., warning lights) automatically upon entry into Fail-safe mode |
| On-chip oscillator supervision | Triggers immediate Fail-safe mode entry if oscillator frequency deviates or stops, preventing silent failures |
Applications
| Body Control Module (BCM) | Engine Control Unit (ECU) |
|---|---|
Use Scenario: Centralized power and communication management for door locks, lighting, and climate actuators in 14 V/42 V vehicle platforms. IC Role / Device Role / Timing Role: UJA1065TW/5V0/C/T acts as the primary system basis chip, supplying regulated 5 V to the BCM MCU, managing CAN/LIN subnets, and enforcing fail-safe shutdown during battery transients. Use Value: Eliminates discrete regulators, watchdogs, and transceivers; reduces BOM count by ≥7 components while enabling ISO 7637-3-compliant transient protection. | Use Scenario: Safety-critical engine management system requiring deterministic startup, watchdog supervision, and fault logging under harsh thermal and EMI conditions. IC Role / Device Role / Timing Role: UJA1065TW/5V0/C/T provides controlled V1 startup, monitors CAN bus integrity, reports overtemperature events via SPI, and activates limp-home output on critical failure. Use Value: Guarantees defined reset behavior after undervoltage events and stores 23 bits of protected diagnostic data for root-cause analysis without external non-volatile memory. |
| Transmission Control Module (TCM) | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
Use Scenario: Transmission control unit interfacing with CAN backbone and LIN-peripheral sensors (e.g., gear position, oil temperature) in dual-voltage architectures. IC Role / Device Role / Timing Role: UJA1065TW/5V0/C/T supplies 5 V to TCM MCU, regulates CAN transceiver power independently, and enables partial networking to reduce bus load during idle states. Use Value: Supports cyclic wake-up via WAKE pin and CAN activity, cutting sleep current to <50 µA while maintaining full diagnostic visibility. | Use Scenario: Central sensor aggregation node connecting radar, camera, and ultrasonic modules via LIN and communicating with domain controller via high-speed CAN. IC Role / Device Role / Timing Role: UJA1065TW/5V0/C/T serves as the power and interface hub, delivering stable 5 V to sensor interface MCU, isolating LIN bus faults from CAN network, and reporting ground shift events. Use Value: Provides two selectable ground shift thresholds and ±60 V bus fault tolerance, eliminating need for external bus protectors in compact ADAS enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fail-safe SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1066TW/5V0/C/T | Includes integrated 3.3 V LDO (V1) instead of 5 V; identical pinout, SPI register map, and fail-safe architecture | Required when host MCU operates at 3.3 V logic; not suitable for 5 V MCU interfaces without level shifting | Select UJA1066TW/5V0/C/T only if MCU supply voltage is 3.3 V; otherwise UJA1065TW/5V0/C/T is required for 5 V MCU compatibility |
| TJA1028TK/5V0/CM | Single-chip LIN SBC without CAN transceiver; includes 5 V VCC regulator, watchdog, and LIN 2.2 transceiver in smaller HVSON14 package | Targeted at LIN-only nodes (e.g., seat control, mirror adjustment); lacks CAN interface and dual-supply BAT14/BAT42 support | Choose TJA1028TK/5V0/CM for cost-sensitive LIN-only applications where CAN connectivity is unnecessary |
Compared with UJA1066TW/5V0/C/T, the UJA1065TW/5V0/C/T provides native 5 V MCU regulation without external level shifters, while versus TJA1028TK/5V0/CM it delivers full CAN+LIN integration and dual-voltage architecture support essential for central ECU roles.
Availability
UJA1065TW/5V0/C/T is available at Aetrix Electronics and suitable for automotive Body Control Modules, Engine Control Units, Transmission Control Modules, and ADAS Sensor Hubs requiring stable component supply, long-term lifecycle assurance, and AEC-Q100 qualified sourcing.
Supply support for UJA1065TW/5V0/C/T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with leadership in CAN, LIN, and functional safety technologies.
The UJA1065 belongs to NXP's System Basis Chip product line, designed specifically for automotive electronic control units requiring integrated power management, fail-safe supervision, and dual-network (CAN+LIN) communication in 14 V/42 V architectures.
FAQ
What is the function of the SPLIT pin on the UJA1065TW/5V0/C/T?
The SPLIT pin on the UJA1065TW/5V0/C/T provides a common-mode stabilization output for the CAN bus, actively regulating the recessive bus voltage level to improve signal integrity and EMC performance. It connects to a split termination resistor network between CANH and CANL, reducing electromagnetic emissions and enhancing noise immunity in automotive harness environments. This feature is integral to the UJA1065TW/5V0/C/T's ISO 11898-2 compliance and distinguishes it from basic CAN transceivers lacking active recessive-level control.
Does the UJA1065TW/5V0/C/T support remote flash programming?
Yes, the UJA1065TW/5V0/C/T supports remote flash programming via the CAN bus using its dedicated Flash mode entry sequence (111-001-111 write to Mode register). This fail-safe mechanism requires hardware handshake confirmation and enforces watchdog supervision during programming, ensuring that corrupted firmware updates do not leave the ECU in an undefined state. The UJA1065TW/5V0/C/T's Flash mode also provides reset source identification (RSS[3:0] = 0110) to distinguish flash operations from other reset events in diagnostic logs.
How does the UJA1065TW/5V0/C/T handle battery voltage transients per ISO 7637-3?
The UJA1065TW/5V0/C/T protects BAT14 and CAN/LIN bus pins against transients in accordance with ISO 7637-3 through integrated clamping circuitry and robust internal ESD structures. Its ±60 V short-circuit proof bus pins and BAT-related inputs withstand pulse 3a/3b transients without external suppressors, while the dedicated V2 regulator for the CAN transceiver remains isolated from V1 to prevent transient coupling into the MCU supply. This design allows direct connection to automotive battery and bus lines in compliance with OEM stress-test requirements.
What is the purpose of the INH/LIMP pin on the UJA1065TW/5V0/C/T?
The INH/LIMP pin on the UJA1065TW/5V0/C/T is a BAT14-referenced push-pull output that serves dual functions: as an inhibit signal to disable external DC-DC converters during low-power modes, and as a limp-home output to activate safety hardware (e.g., warning lights, hazard indicators) when the system enters Fail-safe mode. Its default floating state prevents unintended activation, and its drive strength is optimized for direct connection to automotive-grade loads without external drivers, simplifying ECU board layout and improving system-level fault containment.
Can the UJA1065TW/5V0/C/T operate in 42 V-only automotive architectures?
Yes, the UJA1065TW/5V0/C/T is explicitly designed for 42 V-only architectures via its BAT42 input pin, which supports up to 42 V nominal supply and includes internal protection against load-dump transients. In such configurations, BAT14 is left unconnected or tied to ground, while V3 delivers switched 42 V output for driving high-power loads like relays or solenoids. The device maintains full functionality-including CAN/LIN communication, watchdog supervision, and fail-safe reporting-across the entire 5 V to 42 V input range, meeting requirements for next-generation mild-hybrid vehicle systems.
UJA1065TW/5V0/C/T, Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Networking
- Interface:
- SPI Serial
- Voltage - Supply:
- 5.5V ~ 52V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1065TW/5V0/C/T, FAQ
1.How can I place an order for UJA1065TW/5V0/C/T, through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1065TW/5V0/C/T, on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1065TW/5V0/C/T, reliable?
The price and inventory of UJA1065TW/5V0/C/T, are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1065TW/5V0/C/T, is usually 5 days.
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Once your UJA1065TW/5V0/C/T, order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1065TW/5V0/C/T,?
For technical support, including UJA1065TW/5V0/C/T, datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1065TW/5V0/C/T, requirements.
6.How does Aetrix verify that UJA1065TW/5V0/C/T, is sourced from the original manufacturer or authorized distributors?
All UJA1065TW/5V0/C/T, products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1065TW/5V0/C/T, meets industry standards.
7.What is the process for return or replacement of UJA1065TW/5V0/C/T,?
All UJA1065TW/5V0/C/T, units undergo pre-shipment inspection (PSI). If there is an issue with UJA1065TW/5V0/C/T,, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1065TW/5V0/C/T, part is unused and in its original packaging.
Return procedure for UJA1065TW/5V0/C/T,:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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