NXP Semiconductors UJA1075ATW/5V0WD,1
- Part No.:
- UJA1075ATW/5V0WD,1
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1075ATW/5V0WD,1.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1075ATW/5V0WD,1 from NXP Semiconductors is a high-speed CAN/LIN core System Basis Chip (SBC) integrating a 5 V microcontroller voltage regulator (V1), ISO 11898-2/5-compliant CAN transceiver, LIN 2.2A/SAE J2602 transceiver, advanced window/timeout watchdog, and SPI interface - designed for automotive ECU power and communication management in engine control, body electronics, and chassis modules.
For engineers reviewing the UJA1075ATW/5V0WD,1 datasheet, UJA1075ATW/5V0WD,1 pinout, UJA1075ATW/5V0WD,1 application, or UJA1075ATW/5V0WD,1 equivalent, key selection criteria include its 5 V/250 mA V1 regulator with external PNP extension, dual wake-up inputs with configurable sampling, limp home output for fail-safe operation, and ISO 7637-3 transient-protected CAN/LIN bus pins.
Technical Context
The UJA1075ATW/5V0WD,1 implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp modes with deterministic transitions triggered by VBAT thresholds, wake events, or thermal conditions. Its CAN transceiver features dedicated low-dropout V2 regulator (5 V), SPLIT pin for recessive bus stabilization, and floating bus pins in Off mode.
Power management includes programmable V1 undervoltage reset at 90 % or 70 % of nominal output, selectable external PNP activation thresholds (50/85 mA), and synchronized wake biasing via WBIAS with 16 ms or 64 ms sampling. The watchdog uses an independent on-chip oscillator and supports Window/Timeout/Off modes with 8 ms–4096 ms configurable periods.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V1 Output Voltage | 5.0 V ±2 % - powers microcontroller and peripherals; stable down to 4.5 V VBAT during cranking (ISO 16750-2) |
| V1 Current Capability | 250 mA base; extendable with external PNP transistor - enables heat distribution across PCB for sustained high-load operation |
| CAN Compliance | ISO 11898-2:2003 & ISO 11898-5:2006 - interoperable with TJA1042; supports high-speed CAN up to 1 Mbps |
| LIN Compliance | LIN 2.2A & SAE J2602 - backward compatible to LIN 1.0; low-slope mode reduces EMC emissions |
| Watchdog Type | Advanced independent watchdog with Window/Timeout/Off modes - clocked by on-chip oscillator; default period 128 ms |
| Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm; exposed die pad - optimized thermal resistance for automotive under-hood environments |
| ESD Protection | ±8 kV HBM, ±6 kV IEC 61000-4-2 on CAN/LIN/wake pins - meets stringent automotive EMC requirements |
| Bus Fault Tolerance | ±58 V short-circuit proof on CAN/LIN pins - withstands load dump and battery reverse connection transients |
Pinout & Package
HTSSOP32 package (SOT549-1) with 32 leads, 0.65 mm pitch, 6.1 mm body width, and thermally enhanced exposed die pad soldered to PCB ground for optimal thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Main microcontroller supply output | 5 V regulated output (±2 %); delivers up to 250 mA; supports external PNP extension via VEXCTRL/VEXCC |
| V2 | CAN transceiver supply output | Dedicated 5 V regulator for internal CAN PHY; independent of V1; can be disabled to reduce power |
| RSTN | Bidirectional reset I/O | Drives microcontroller reset; accepts external reset signal; programmable power-on reset length |
| INTN | Interrupt output | Open-drain output signaling V1/V2 undervoltage, CAN/LIN/local wake-up, cyclic, or power-on events |
| WAKE1 / WAKE2 | Local wake-up analog inputs | Configurable wake sources with selectable 16 ms/64 ms sampling via WBIAS; support switch-based sensor wake |
| LIMP | Limp home control output | Active-low output to activate fail-safe hardware during critical faults (e.g., overtemperature or system crash) |
| SPLIT | CAN common-mode stabilization | Output for external 4.7 nF capacitor to stabilize recessive bus level and reduce ringing |
| WDOFF | Watchdog disable input | Hardware disable of watchdog; HIGH level forces immediate watchdog shutdown and software reset |
Key Features
| Feature | Design Value |
|---|---|
| Integrated CAN + LIN transceivers | Eliminates discrete transceiver components while maintaining full ISO/SAE compliance and bus fault tolerance |
| Scalable 5 V/250 mA V1 regulator | Supports demanding microcontrollers; external PNP extension allows >1 A total current with distributed thermal load |
| Programmable watchdog with independent clock | Prevents runaway code without relying on MCU clock; window mode detects both early and late triggers for robust safety |
| Full-duplex SPI interface | Enables real-time configuration, status reporting, and diagnostics between SBC and MCU without shared memory or complex protocols |
| Multi-source wake-up capability | Simultaneous wake detection from CAN bus activity, LIN bus activity, or two local digital/analog inputs - ensures reliable ECU responsiveness |
| Fail-safe limp home output | Direct hardware assertion of LIMP pin during overtemperature or critical failure - enables immediate mechanical or functional fallback |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Centralized power and communication management for diesel/gasoline engine controllers handling fuel injection, ignition timing, and OBD-II diagnostics. IC Role / Device Role / Timing Role: Core SBC providing controlled MCU startup, CAN-based actuator control, LIN-sensor network interfacing, and watchdog-monitored safe operation. Use Value: Ensures deterministic boot sequence, survives cranking (VBAT ≥ 4.5 V), and maintains CAN/LIN connectivity during ISO 7637-2 pulses - critical for ASIL-B functional safety compliance. | Use Scenario: Power and networking hub for door modules, lighting, HVAC, and seat controls in modern vehicle architectures. IC Role / Device Role / Timing Role: Supplies 5 V to body MCU, manages LIN slave nodes (e.g., window lifters), monitors wake events from door switches, and asserts LIMP on thermal fault. Use Value: Reduces BOM count by integrating regulators, transceivers, and watchdog; 16 ms wake sampling enables ultra-low standby current (< 30 µA) while retaining fast response. |
| Chassis Control Unit | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
Use Scenario: Safety-critical ABS/ESC module requiring redundant power supervision and fail-operational behavior under voltage transients. IC Role / Device Role / Timing Role: Delivers stable V1/V2 supplies, monitors CAN bus integrity, triggers system reset on V1 undervoltage (90 % threshold), and activates LIMP output on OTP event. Use Value: Dual undervoltage detection (90 % warning + 70 % reset) and ±58 V bus tolerance ensure uninterrupted operation during load dump and jump-start scenarios. | Use Scenario: Aggregation node for radar, camera, and ultrasonic sensors communicating via CAN and LIN in domain-controller architectures. IC Role / Device Role / Timing Role: Provides isolated 5 V power to sensor MCUs, routes CAN commands to actuators, relays LIN sensor data, and reports thermal/voltage faults via SPI. Use Value: SPLIT pin stabilization and low-slope LIN mode minimize electromagnetic interference near sensitive RF receivers - meeting CISPR 25 Class 5 limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar core SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1043TK/0Z | Standalone high-speed CAN transceiver only - no LIN, no regulators, no watchdog, no SPI | Requires external LIN transceiver, voltage regulators, and watchdog IC - increases BOM, layout area, and validation effort | Select when only CAN physical layer is needed and system-level power/communication integration is handled elsewhere |
| UJA1076ATW/5V0WD,1 | Same footprint and pinout; adds integrated 3.3 V LDO for CAN FD controller - V1 remains 5 V/250 mA | Enables direct interface to CAN FD microcontrollers without external level-shifting; same automotive qualification and thermal specs | Select when migrating to CAN FD while retaining identical power architecture and fail-safe features |
Compared with TJA1043TK/0Z, UJA1075ATW/5V0WD,1 reduces component count and improves system-level reliability through integration; compared with UJA1076ATW/5V0WD,1, it omits the secondary 3.3 V LDO - simplifying design where CAN FD is not required and cost optimization is prioritized.
Availability
UJA1075ATW/5V0WD,1 is available at Aetrix Electronics and suitable for automotive engine control, body electronics, chassis systems, and ADAS sensor hubs requiring stable component supply, long-term lifecycle support, and AEC-Q100 qualified parts.
Supply support for UJA1075ATW/5V0WD,1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade mixed-signal ICs and functional safety certification.
The UJA1075ATW/5V0WD,1 belongs to NXP's System Basis Chip portfolio - engineered specifically for automotive ECU consolidation, delivering integrated power, communication, and safety functions in a single AEC-Q100 qualified device.
FAQ
What is the primary function of the UJA1075ATW/5V0WD,1 in an automotive ECU?
The UJA1075ATW/5V0WD,1 serves as a core System Basis Chip that integrates power regulation (5 V/250 mA V1 and dedicated 5 V V2), high-speed CAN and LIN transceivers, an advanced watchdog, SPI interface, and fail-safe features like LIMP output. It replaces multiple discrete components to manage MCU power-up, communication, wake-up, and fault response - all within a single AEC-Q100 qualified HTSSOP32 package.
Does the UJA1075ATW/5V0WD,1 support both CAN and LIN networks simultaneously?
Yes, the UJA1075ATW/5V0WD,1 supports concurrent operation of high-speed CAN (ISO 11898-2/5 compliant) and LIN (LIN 2.2A/SAE J2602 compliant) networks. Its dual transceivers operate independently - CAN handles high-priority actuator control, while LIN manages low-cost sensor nodes - with separate regulators (V1 for MCU, V2 for CAN PHY) and shared SPI for coordinated configuration and status reporting.
How does the watchdog in UJA1075ATW/5V0WD,1 differ from basic timeout watchdogs?
The UJA1075ATW/5V0WD,1 features an advanced independent watchdog with Window, Timeout, and Off modes, clocked by an on-chip oscillator unrelated to V1/V2. Unlike basic timeout watchdogs, its Window mode requires triggers within a defined time window - detecting both early (premature) and late (missed) resets to prevent malicious or erratic firmware behavior. Default period is 128 ms, configurable from 8 ms to 4096 ms via SPI.
Can the UJA1075ATW/5V0WD,1 operate during automotive cranking conditions?
Yes, the UJA1075ATW/5V0WD,1 is designed for automotive cranking: its V1 regulator maintains stable 5 V output down to 4.5 V VBAT (per ISO 16750-2), and V2 operates down to 5.5 V VBAT (per ISO 7637). This ensures continuous MCU power, CAN/LIN communication, and watchdog supervision even during engine start when battery voltage dips transiently.
What is the purpose of the SPLIT pin on the UJA1075ATW/5V0WD,1?
The SPLIT pin on the UJA1075ATW/5V0WD,1 provides a common-mode stabilization output for the CAN bus. When connected to a 4.7 nF capacitor to ground, it actively stabilizes the recessive bus level (CANH/CANL midpoint), reducing signal ringing caused by bus reflections - especially critical in longer or unterminated CAN networks. This improves signal integrity and EMC performance without requiring external active components.
UJA1075ATW/5V0WD,1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Applications:
- -
- Interface:
- CAN, LIN
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1075ATW/5V0WD,1 FAQ
1.How can I place an order for UJA1075ATW/5V0WD,1 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1075ATW/5V0WD,1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1075ATW/5V0WD,1 reliable?
The price and inventory of UJA1075ATW/5V0WD,1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1075ATW/5V0WD,1 is usually 5 days.
3.What payment methods are accepted for UJA1075ATW/5V0WD,1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1075ATW/5V0WD,1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1075ATW/5V0WD,1?
UJA1075ATW/5V0WD,1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1075ATW/5V0WD,1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1075ATW/5V0WD,1?
For technical support, including UJA1075ATW/5V0WD,1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1075ATW/5V0WD,1 requirements.
6.How does Aetrix verify that UJA1075ATW/5V0WD,1 is sourced from the original manufacturer or authorized distributors?
All UJA1075ATW/5V0WD,1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1075ATW/5V0WD,1 meets industry standards.
7.What is the process for return or replacement of UJA1075ATW/5V0WD,1?
All UJA1075ATW/5V0WD,1 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1075ATW/5V0WD,1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1075ATW/5V0WD,1 part is unused and in its original packaging.
Return procedure for UJA1075ATW/5V0WD,1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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