NXP Semiconductors UJA1075ATW/5V0/WDJ
- Part No.:
- UJA1075ATW/5V0/WDJ
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1075ATW/5V0/WDJ.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,000
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Product details
Overview
UJA1075ATW/5V0/WDJ from NXP Semiconductors is a high-speed CAN/LIN core System Basis Chip (SBC) integrating a 5 V/250 mA microcontroller voltage regulator (V1), ISO 11898-2/5-compliant CAN transceiver, LIN 2.2A/SAE J2602 transceiver, advanced window/timeout watchdog, and full-duplex SPI interface - designed for automotive ECU power management and network interface consolidation.
For engineers reviewing the UJA1075ATW/5V0/WDJ datasheet, UJA1075ATW/5V0/WDJ pinout, UJA1075ATW/5V0/WDJ application, or UJA1075ATW/5V0/WDJ equivalent, key selection criteria include its 5 V V1 regulator with ±2 % accuracy, dual wake-up inputs (WAKE1/WAKE2), limp home output (LIMP), SPLIT pin for CAN bus stabilization, and HTSSOP32 package with exposed thermal pad.
Technical Context
The UJA1075ATW/5V0/WDJ implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp modes with deterministic transitions triggered by VBAT thresholds, wake events, or register writes. Its CAN transceiver features dedicated low-dropout V2 regulator (5 V), floating bus pins in Off mode, and SPLIT output for recessive-level stabilization.
Power management includes programmable V1 undervoltage reset at 90 % or 70 % of nominal output, selectable external PNP transistor activation thresholds (50/85 mA), and synchronized 16/64 ms wake-up sampling via WBIAS. The watchdog uses an independent on-chip oscillator and supports Window/Timeout/Off modes with configurable periods from 8 ms to 4096 ms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V1 Output Voltage | 5.0 V ±2 % - powers microcontroller and peripherals with stable regulation down to 4.5 V VBAT (cranking compliant) |
| V1 Max Current | 250 mA - extendable with external PNP transistor for thermal distribution across PCB |
| CAN Compliance | ISO 11898-2:2003 & ISO 11898-5:2006 - interoperable with TJA1042; bus pins withstand ±58 V short-circuit and ISO 7637-3 transients |
| LIN Compliance | LIN 2.2A & SAE J2602 - downward compatible to LIN 1.0; integrated termination diode at DLIN pin |
| Watchdog Modes | Window, Timeout, Off - clocked by independent on-chip oscillator; default period 128 ms; WDOFF pin disables it in hardware |
| SPI Interface | Full-duplex 16-bit - supports read-only register access and status reporting during control writes |
| Thermal Protection | Overtemperature shutdown - triggers LIMP output LOW and forces reset when chip exceeds Tth(act)otp |
Pinout & Package
Package: HTSSOP32 (SOT549-1), 6.1 mm × 11 mm, 0.65 mm pitch, exposed thermal pad soldered to PCB ground for enhanced thermal/electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Main microcontroller supply output | 5 V regulated output (±2 %); supports external PNP extension via VEXCTRL/VEXCC |
| V2 | CAN transceiver supply output | Dedicated 5 V regulator for internal CAN PHY; independent of V1, improves EMC |
| RSTN | Bidirectional reset I/O | Drives microcontroller reset; variable power-on pulse length (long/short); supports software-initiated reset |
| INTN | Interrupt output | Open-drain signal for V1/V2 undervoltage, CAN/LIN/wake-up, cyclic, and power-on events |
| LIMP | Limp home control output | Active-low output to activate fail-safe hardware during critical system faults or overtemperature |
| SPLIT | CAN bus common-mode stabilizer | Output for external RC network to reduce ringing and stabilize recessive bus level |
| WAKE1 / WAKE2 | Local wake-up analog inputs | Configurable sampling (16/64 ms); bias controlled by WBIAS; support switch debouncing in Standby |
| WDOFF | Hardware watchdog disable input | Pull HIGH to permanently disable watchdog - overrides all register settings |
Key Features
| Feature | Design Value |
|---|---|
| Integrated CAN + LIN transceivers | Eliminates discrete transceiver components; enables single-chip ECU networking with bus-level fault protection |
| Scalable V1 regulator with PNP extension | 250 mA base current + external PNP allows >1 A total while distributing heat across PCB layers |
| Advanced low-power architecture | Standby current < 100 µA and Sleep current < 20 µA - maintains full wake-up capability via CAN/LIN/local pins |
| Robust automotive qualification | ±8 kV HBM ESD on bus/wake pins; ±6 kV IEC 61000-4-2; ISO 7637-3 transient immunity; AEC-Q100 Grade 1 qualified |
| Comprehensive diagnostics & control | SPI-accessible registers for real-time monitoring of V1/V2 status, wake sources, interrupt flags, and limp home state |
Applications
| Body Control Module (BCM) | Engine Control Unit (ECU) |
|---|---|
|
Use Scenario: Centralized power and communication management for door locks, lighting, and climate actuators. IC Role / Device Role / Timing Role: Core SBC providing 5 V microcontroller supply, CAN backbone connectivity, and LIN sub-bus for sensors/actuators. Use Value: Reduces BOM count by replacing discrete regulators, CAN/LIN transceivers, and watchdog ICs; supports remote flash programming via CAN. |
Use Scenario: Power sequencing and network interface for engine management MCU under cranking conditions. IC Role / Device Role / Timing Role: Ensures controlled startup and safe shutdown; delivers stable 5 V V1 supply down to 4.5 V VBAT. Use Value: Maintains microcontroller operation during cold-crank events; enables limp-home activation via LIMP pin on critical failure. |
| Transmission Control Unit (TCU) | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
|
Use Scenario: Power and communication interface for gear-shifting logic and solenoid drivers. IC Role / Device Role / Timing Role: Supplies 5 V MCU and peripherals; provides CAN for vehicle network integration and LIN for local valve position feedback. Use Value: Dual wake-up inputs (WAKE1/WAKE2) enable precise timing of gear-shift readiness signals; SPLIT pin minimizes CAN bus reflections in noisy transmission environments. |
Use Scenario: Consolidated power and interface for radar/camera sensor clusters requiring low EMI and fail-safe behavior. IC Role / Device Role / Timing Role: Delivers clean 5 V supply with ±2 % accuracy; provides LIN for sensor configuration and CAN for data aggregation. Use Value: High EMC robustness (±6 kV IEC 61000-4-2) prevents false wake-ups; overtemperature shutdown with LIMP assertion ensures functional safety compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar core SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1023TK/0Z | Single-channel LIN transceiver only; no CAN, no V1/V2 regulators, no watchdog - requires external power and interface ICs | Used for LIN-only nodes (e.g., mirror controls); lacks ECU-level integration | Select when only LIN interface is needed and system already has separate CAN transceiver and power management |
| UJA1169ATW/5V0/3 | Includes 3.3 V V1 regulator (not 5 V); adds embedded high-side switch and improved CAN ESD (±10 kV); same HTSSOP32 footprint | Targeted at newer 3.3 V MCU platforms with higher integration (e.g., integrated load switch for pre-charge control) | Choose for 3.3 V systems requiring higher bus robustness and load switching; not drop-in due to V1 voltage mismatch |
Compared with UJA1075ATW/5V0/WDJ, TJA1023TK/0Z offers minimal integration and requires full external support circuitry, while UJA1169ATW/5V0/3 targets 3.3 V designs with added functionality but cannot substitute directly due to regulator voltage mismatch and different feature set.
Availability
UJA1075ATW/5V0/WDJ is available at Aetrix Electronics and suitable for automotive body control modules, engine control units, transmission control units, and ADAS sensor hubs requiring stable component supply, long lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for UJA1075ATW/5V0/WDJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade mixed-signal ICs and functional safety design.
The UJA1075ATW/5V0/WDJ belongs to NXP's System Basis Chip product line, engineered specifically to consolidate power management, high-speed CAN, and LIN networking functions into a single AEC-Q100-qualified device for next-generation automotive ECUs.
FAQ
What is the nominal output voltage and accuracy of the main regulator (V1) in UJA1075ATW/5V0/WDJ?
The UJA1075ATW/5V0/WDJ features a 5.0 V main voltage regulator (V1) with ±2 % output voltage accuracy across temperature and load. This precision enables reliable operation of automotive microcontrollers and peripherals without external trimming. The regulator maintains regulation down to 4.5 V battery input, meeting ISO 16750-2 cranking requirements. UJA1075ATW/5V0/WDJ also supports undervoltage warning at 90 % of nominal output and configurable reset thresholds at either 90 % or 70 % of nominal.
Does UJA1075ATW/5V0/WDJ support both CAN and LIN communication simultaneously?
Yes, UJA1075ATW/5V0/WDJ integrates fully independent high-speed CAN and LIN physical layers that operate concurrently. The CAN transceiver complies with ISO 11898-2:2003 and ISO 11898-5:2006, while the LIN transceiver meets LIN 2.2A and SAE J2602 standards. Both interfaces can be active in Normal mode, or individually placed in Lowpower mode with wake-up detection enabled - allowing UJA1075ATW/5V0/WDJ to serve as the central networking hub in multi-bus automotive ECUs without resource contention.
How does the watchdog function in UJA1075ATW/5V0/WDJ, and what are its operational modes?
The UJA1075ATW/5V0/WDJ incorporates an advanced independent watchdog with three configurable modes: Window, Timeout, and Off. It uses an on-chip oscillator for timing independence from V1/V2 supplies. The watchdog period is programmable from 8 ms to 4096 ms via the NWP bits in the WD_and_Status register. In Window mode, triggering outside the defined window causes immediate reset; in Timeout mode, overflow triggers reset. UJA1075ATW/5V0/WDJ also supports hardware disable via the WDOFF pin, which overrides all register settings.
What is the purpose of the SPLIT pin on UJA1075ATW/5V0/WDJ, and how is it used?
The SPLIT pin on UJA1075ATW/5V0/WDJ provides a dedicated output for stabilizing the recessive common-mode voltage on the CAN bus. It connects to an external RC network (typically 60 Ω resistor + 470 pF capacitor to GND) to dampen bus reflections and reduce electromagnetic emissions. This feature enhances signal integrity in electrically noisy automotive environments and is especially valuable in longer bus topologies or systems with multiple stubs. Unlike generic CAN transceivers, UJA1075ATW/5V0/WDJ integrates this functionality to improve EMC without requiring external active components.
Can UJA1075ATW/5V0/WDJ operate during automotive battery cranking conditions?
Yes, UJA1075ATW/5V0/WDJ is explicitly designed for automotive cranking conditions. Its V1 regulator operates stably down to 4.5 V VBAT, complying with ISO 16750-2 and ISO 7637-2 specifications. The V2 regulator for the CAN transceiver remains functional down to 5.5 V VBAT. Both regulators maintain output stability and continue supporting microcontroller and transceiver operation during engine start-up voltage dips. UJA1075ATW/5V0/WDJ also includes undervoltage detection and reset functionality to ensure deterministic behavior throughout cranking events.
UJA1075ATW/5V0/WDJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Applications:
- -
- Interface:
- CAN, LIN
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1075ATW/5V0/WDJ FAQ
1.How can I place an order for UJA1075ATW/5V0/WDJ through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1075ATW/5V0/WDJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1075ATW/5V0/WDJ reliable?
The price and inventory of UJA1075ATW/5V0/WDJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1075ATW/5V0/WDJ is usually 5 days.
3.What payment methods are accepted for UJA1075ATW/5V0/WDJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1075ATW/5V0/WDJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1075ATW/5V0/WDJ?
UJA1075ATW/5V0/WDJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1075ATW/5V0/WDJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1075ATW/5V0/WDJ?
For technical support, including UJA1075ATW/5V0/WDJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1075ATW/5V0/WDJ requirements.
6.How does Aetrix verify that UJA1075ATW/5V0/WDJ is sourced from the original manufacturer or authorized distributors?
All UJA1075ATW/5V0/WDJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1075ATW/5V0/WDJ meets industry standards.
7.What is the process for return or replacement of UJA1075ATW/5V0/WDJ?
All UJA1075ATW/5V0/WDJ units undergo pre-shipment inspection (PSI). If there is an issue with UJA1075ATW/5V0/WDJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1075ATW/5V0/WDJ part is unused and in its original packaging.
Return procedure for UJA1075ATW/5V0/WDJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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