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NXP Semiconductors UJA1075TW/3V3,112
- Part No.:
- UJA1075TW/3V3,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1075TW/3V3,112.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,982
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Product details
Overview
UJA1075TW/3V3,112 from NXP Semiconductors is a core System Basis Chip (SBC) integrating high-speed CAN and LIN transceivers, a 3.3 V/250 mA microcontroller voltage regulator (V1), a dedicated 5 V CAN transceiver regulator (V2), SPI interface, dual local wake-up inputs, and limp home output - designed for automotive ECU power and communication management in engine control, body electronics, and chassis modules.
For engineers reviewing the UJA1075TW/3V3,112 datasheet, UJA1075TW/3V3,112 pinout, UJA1075TW/3V3,112 application, or UJA1075TW/3V3,112 equivalent, this page delivers verified functional architecture, automotive-grade EMC/ESD specs, thermal-safe regulator operation down to 4.5 V battery input, ISO 11898-2/ISO 11898-5 and LIN 2.1 compliance, and precise mode-control state transitions for robust ECU startup and fault recovery.
Technical Context
The UJA1075TW/3V3,112 implements a deterministic state-machine system controller managing Off/Standby/Normal/Sleep/Overtemp modes with programmable entry/exit conditions, including VBAT threshold detection (Vth(det)pon = ~5.5 V, Vth(det)poff = ~2.7 V), MC register-controlled mode selection, and automatic reset generation on wake-up or overtemperature events.
Its dual-regulator architecture isolates V1 (3.3 V ±2 % for LIN master, ±3 % for LIN slave) from V2 (5 V for CAN transceiver), enabling independent undervoltage monitoring (90 % V1/V2 warning, 90 % or 70 % V1 reset threshold), external PNP extension for V1 current scaling (Ith(act)PNP = 50–85 mA), and SPLIT pin stabilization of CAN recessive bus level per ISO 11898-2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Interface | High-speed CAN transceiver compliant with ISO 11898-2 and ISO 11898-5; supports active bus wake-up and floating bus pins when powered off. |
| LIN Interface | LIN 2.1 transceiver compliant with SAE J2602 and backward-compatible with LIN 2.0/LIN 1.3; includes low-slope mode and integrated DLIN termination diode. |
| V1 Regulator Output | 3.3 V ±2 % (LIN master) / ±3 % (LIN slave); delivers up to 250 mA; supports external PNP transistor for thermal distribution and current scaling. |
| V2 Regulator Output | 5 V dedicated supply for internal CAN transceiver; undervoltage warning at 90 % nominal; switchable off to reduce power in Standby mode. |
| SPI Interface | Full-duplex 16-bit SPI with SCSN/SCK/SDI/SDO signals; supports read-only register access and status reporting during configuration writes. |
| Wake-up Capability | Dual local wake-up inputs (WAKE1/WAKE2) with configurable sampling (16 ms or 64 ms), plus CAN/LIN bus wake-up detection in Lowpower mode. |
| Thermal Protection | Overtemperature shutdown with hysteresis; LIMP output driven LOW upon OTP activation; automatic return to Standby mode after chip cools below Tth(rel)otp. |
Pinout & Package
Package: HTSSOP32 (SOT549-1), 6.1 mm × 11 mm, 0.65 mm pitch, exposed die pad for PCB thermal dissipation (electrically isolated, may be left floating or connected to GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Main microcontroller supply output | 3.3 V regulated output; powers MCU and peripherals; supports external PNP extension via VEXCTRL/VEXCC pins. |
| V2 | CAN transceiver supply output | 5 V dedicated regulator output; electrically isolated from V1 to improve EMC and enable independent shutdown. |
| RSTN | Bidirectional reset I/O | Drives LOW during power-on, watchdog overflow, or overtemperature; accepts variable-length reset pulse from MCU. |
| INTN | Interrupt output | Open-drain signal indicating V1/V2 undervoltage, CAN/LIN/local wake-up, cyclic, or power-on events; individually maskable. |
| WAKE1 / WAKE2 | Local wake-up inputs | Configurable edge-sensitive inputs with bias control via WBIAS; support synchronized sampling to reduce standby current. |
| LIMP | Limp home control output | Active-LOW output activated during Overtemp mode or software-triggered limp home; drives external fail-safe hardware. |
| SPLIT | CAN common-mode stabilization | Output for external 47 Ω resistor to stabilize recessive bus level; required for ISO 11898-2-compliant bus termination. |
| TXDC / RXDC | CAN data interface | Digital-level inputs/outputs connecting to MCU's CAN controller; isolated from physical bus by integrated transceiver. |
| TXDL / RXDL | LIN data interface | Digital-level inputs/outputs connecting to MCU's LIN controller; DLIN pin provides internal termination diode connection. |
| BAT | Battery supply input | Primary input (4.5 V to 40 V); powers all regulators and logic; protected per ISO 7637-3 transient standards. |
Key Features
| Feature | Design Value |
|---|---|
| Automotive-grade EMC/ESD protection | ±8 kV HBM and ±6 kV IEC 61000-4-2 ESD on CAN/LIN/wake pins; ±58 V short-circuit proof bus pins; ISO 7637-3 transient immunity. |
| Intelligent power sequencing | Controlled start-up behavior with mode-state machine (Off→Standby→Normal); safe reset assertion during cranking (VBAT ≥ 4.5 V). |
| Flexible watchdog operation | Programmable Window/Timeout/Off modes with on-chip oscillator clock; NWP bits set default period to 128 ms; WDOFF pin disables watchdog independently. |
| Thermally optimized regulator design | V1 regulator supports external PNP transistor (via VEXCTRL/VEXCC) to distribute heat across PCB; exposed die pad enhances thermal conduction. |
| Comprehensive diagnostics | SPI-accessible registers (WD_and_Status, Mode_Control, Int_Status) provide real-time visibility into V1/V2 status, wake sources, interrupt flags, and limp home state. |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Centralized engine management unit requiring CAN-based communication with sensors/actuators and LIN-connected sub-peripherals (e.g., throttle valve, coolant sensor). IC Role / Device Role / Timing Role: Core SBC providing regulated 3.3 V power to MCU, isolated 5 V for CAN transceiver, LIN physical layer, and wake-up supervision for ignition-on/off transitions. Use Value: Enables single-chip integration of power, CAN, and LIN functions while maintaining ISO 11898-2 and LIN 2.1 compliance, reducing BOM count and improving cranking resilience (VBAT down to 4.5 V). | Use Scenario: Vehicle body electronics module controlling door locks, lighting, and HVAC via LIN slaves and communicating with gateway via high-speed CAN. IC Role / Device Role / Timing Role: Power and interface hub supplying 3.3 V to body MCU, managing LIN bus timing and wake-up events from door switches or key fob receivers, and signaling faults via LIMP output. Use Value: Delivers precise 3.3 V regulation (±2 % for LIN master) and low-slope LIN mode for EMC-robust interior wiring, with dual wake-up inputs supporting multiple mechanical switch interfaces. |
| Chassis Control System | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
Use Scenario: ABS/ESC control unit needing reliable CAN communication, localized LIN connectivity for wheel speed sensors, and fail-safe response to thermal overload. IC Role / Device Role / Timing Role: Safety-critical SBC delivering stable V1/V2 supplies, detecting overtemperature via on-die sensor, and asserting LIMP output to activate mechanical brake fallback. Use Value: Provides certified overtemperature shutdown with hysteresis and LIMP-driven hardware activation-meeting ASIL-B-relevant functional safety requirements without external supervision. | Use Scenario: Radar or camera sensor node requiring low-quiescent-power sleep mode, wake-on-CAN command, and precise voltage regulation for analog front-end stability. IC Role / Device Role / Timing Role: Low-power SBC enabling Sleep mode with <10 µA current, bus wake-up detection, and fast V1 reactivation (<100 ms) upon CAN message reception. Use Value: Achieves ultra-low sleep current while retaining full wake-up capability via CAN/LIN/local inputs-critical for always-on ADAS nodes with strict energy budgets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1043TK/3V3/1 | Single high-speed CAN transceiver only; no LIN, no V1/V2 regulators, no SPI or watchdog. | Requires external LIN transceiver, voltage regulators, and system supervisor ICs to replicate UJA1075TW/3V3,112 functionality. | Select when only CAN physical layer is needed and system-level integration is handled separately. |
| MC33816AEKR2 | 3.3 V/250 mA regulator + CAN transceiver + watchdog; no LIN interface; different SPI register map and wake-up architecture. | Lacks native LIN 2.1 support and DLIN termination; requires external LIN transceiver and modified firmware for wake-up handling. | Choose for CAN-only designs where NXP ecosystem compatibility is not required and LIN is implemented externally. |
Compared with UJA1075TW/3V3,112, TJA1043TK/3V3/1 offers only physical-layer CAN connectivity, demanding significant external components for full ECU functionality, while MC33816AEKR2 provides partial integration but omits LIN-making UJA1075TW/3V3,112 uniquely suited for cost- and space-constrained dual-bus automotive ECUs requiring single-chip power, CAN, and LIN convergence.
Availability
UJA1075TW/3V3,112 is available at Aetrix Electronics and suitable for engine control units, body control modules, and chassis systems requiring stable component supply, automotive qualification, and long-term lifecycle support.
Supply support for UJA1075TW/3V3,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with leadership in CAN, LIN, and automotive power management ICs.
The UJA1075TW/3V3,112 belongs to NXP's System Basis Chip product line, engineered specifically for automotive electronic control units requiring integrated high-speed CAN, LIN, power regulation, and fail-safe supervision in a single package.
FAQ
What is the operating voltage range for UJA1075TW/3V3,112 battery input (BAT pin)?
The UJA1075TW/3V3,112 supports a battery input range of 4.5 V to 40 V. It maintains stable V1 (3.3 V) and V2 (5 V) regulation down to 4.5 V-enabling reliable operation during engine cranking per ISO 7637-2 Pulse 4b and ISO 16750-2 cold-cranking profiles. Transient protection complies with ISO 7637-3.
Does UJA1075TW/3V3,112 include a watchdog timer, and how is it configured?
Yes, UJA1075TW/3V3,112 includes a programmable watchdog with Window, Timeout, and Off modes. It is clocked by an on-chip oscillator and configured via the WD_and_Status register (bits WMC and NWP). The default watchdog period is 128 ms. Pin WDOFF provides hardware disable capability independent of register settings.
How does the UJA1075TW/3V3,112 support LIN 2.1 compliance and EMC robustness?
The UJA1075TW/3V3,112 integrates a LIN 2.1 transceiver compliant with SAE J2602 and backward-compatible with LIN 2.0/1.3. It supports low-slope mode (10.4 kbit/s) for improved EMC and includes an integrated termination diode at DLIN. Its ±6 kV IEC 61000-4-2 ESD rating on LIN pins further ensures robustness in noisy vehicle environments.
Can the 3.3 V regulator (V1) of UJA1075TW/3V3,112 be extended beyond 250 mA, and how?
Yes, the V1 regulator of UJA1075TW/3V3,112 can be extended beyond 250 mA using an external PNP transistor. Pins VEXCTRL (base drive) and VEXCC (collector current sense) enable controlled current sharing. Thresholds for PNP activation/deactivation (e.g., 50 mA/15 mA or 85 mA/50 mA) are selectable via the PDC bit in the Mode_Control register.
What happens to the UJA1075TW/3V3,112 during overtemperature conditions?
When die temperature exceeds the OTP activation threshold (Tth(act)otp), the UJA1075TW/3V3,112 enters Overtemp mode: V1 and V2 regulators shut down, bus transceivers enter high-impedance state, RSTN is driven LOW, and LIMP is asserted LOW. Recovery occurs only after temperature falls below the release threshold (Tth(rel)otp), triggering automatic return to Standby mode with system reset.
UJA1075TW/3V3,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- CAN, LIN
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1075TW/3V3,112 FAQ
1.How can I place an order for UJA1075TW/3V3,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1075TW/3V3,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1075TW/3V3,112 reliable?
The price and inventory of UJA1075TW/3V3,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1075TW/3V3,112 is usually 5 days.
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Once your UJA1075TW/3V3,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1075TW/3V3,112?
For technical support, including UJA1075TW/3V3,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1075TW/3V3,112 requirements.
6.How does Aetrix verify that UJA1075TW/3V3,112 is sourced from the original manufacturer or authorized distributors?
All UJA1075TW/3V3,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1075TW/3V3,112 meets industry standards.
7.What is the process for return or replacement of UJA1075TW/3V3,112?
All UJA1075TW/3V3,112 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1075TW/3V3,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1075TW/3V3,112 part is unused and in its original packaging.
Return procedure for UJA1075TW/3V3,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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