NXP Semiconductors UJA1075TW/3V3,118
- Part No.:
- UJA1075TW/3V3,118
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1075TW/3V3,118.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,842
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UJA1075TW/3V3,118 from NXP Semiconductors is a core System Basis Chip (SBC) integrating a high-speed CAN transceiver (ISO 11898-2/5 compliant), LIN 2.1 transceiver (SAE J2602 compliant), 3.3 V/250 mA microcontroller voltage regulator (V1), dedicated 5 V CAN transceiver regulator (V2), SPI interface, dual local wake-up inputs, and limp home output - deployed in automotive Electronic Control Units for centralized power, communication, and safety management.
For engineers reviewing the UJA1075TW/3V3,118 datasheet, UJA1075TW/3V3,118 pinout, UJA1075TW/3V3,118 application, or UJA1075TW/3V3,118 equivalent, key selection considerations include 3.3 V V1 regulator accuracy (±2 % for LIN master), CAN/LIN bus ESD protection (±8 kV HBM), thermal shutdown behavior, HTSSOP32 package pin compatibility, and watchdog configuration via SPI register WD_and_Status.
Technical Context
The UJA1075TW/3V3,118 implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp mode transitions triggered by VBAT thresholds, wake events, or temperature. Its dual-regulator architecture isolates V1 (3.3 V, 250 mA) for MCU/peripherals from V2 (5 V) dedicated to the CAN transceiver - enabling independent undervoltage monitoring (90 % Vuvd reset threshold) and cranking operation down to 4.5 V.
SPI communication uses full-duplex protocol with SCSN-active-low, falling-edge sampling, and register-mapped control (e.g., Mode_Control at address 001, WD_and_Status at 000). The integrated watchdog operates in Window/Timeout/Off modes with programmable periods (8–4096 ms) and independent on-chip oscillator timing, while LIN slope control (10.4/20 kbit/s) and CAN SPLIT output stabilize bus common-mode levels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Interface | High-speed ISO 11898-2/5 compliant; supports active/low-power bus states with wake-up detection and SPLIT pin for recessive level stabilization. |
| LIN Interface | LIN 2.1 & SAE J2602 compliant; backward compatible with LIN 2.0/1.3; low-slope mode (10.4 kbit/s) for EMC optimization. |
| V1 Regulator | 3.3 V ±2 % (LIN master), ±3 % (LIN slave); 250 mA max; supports external PNP transistor for thermal distribution; operates down to 4.5 V VBAT. |
| V2 Regulator | 5 V dedicated supply for internal CAN transceiver; undervoltage warning at 90 % nominal; switchable off; operates down to 5.5 V VBAT. |
| Watchdog | Programmable Window/Timeout/Off modes; 8–4096 ms period via NWP bits; independent on-chip oscillator; WDOFF pin disables globally. |
| SPI Interface | Full-duplex, 16-bit; SCSN-active-low, falling-edge sampling; register map includes WD_and_Status (000), Mode_Control (001), Int_Control (010). |
| Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm; 0.65 mm pitch; exposed die pad for PCB thermal dissipation; RoHS/dark green compliant. |
Pinout & Package
UJA1075TW/3V3,118 is housed in a 32-pin HTSSOP package (SOT549-1) with 6.1 mm body width, 0.65 mm lead pitch, and an exposed die pad for enhanced thermal conduction to the PCB. The die pad is electrically isolated and may be left floating or connected to GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 (Pin 4) | Main MCU supply output | 3.3 V regulated output; ±2 % accuracy for LIN master; supports external PNP biasing via VEXCTRL/VEXCC. |
| V2 (Pin 20) | CAN transceiver supply | Dedicated 5 V regulator; independent of V1; enables CAN operation during V1 brownout. |
| RSTN (Pin 6) | Bidirectional reset I/O | Drives LOW during overtemperature, V1/V2 undervoltage, or watchdog overflow; configurable reset pulse length. |
| INTN (Pin 7) | Interrupt output | Open-drain signal indicating V1/V2 undervoltage, CAN/LIN/local wake-up, cyclic, or power-on events. |
| WAKE1/WAKE2 (Pins 18/19) | Local wake-up inputs | Configurable edge-triggered inputs; sampling synchronized to WBIAS (16/64 ms) when enabled. |
| LIMP (Pin 17) | Limp home activation | Active-LOW output asserting hardware fail-safe mode during critical faults (e.g., overtemperature). |
| SPLIT (Pin 24) | CAN common-mode stabilizer | Connects to external 4.7 nF capacitor to reduce CAN bus reflections and improve EMC. |
| BAT (Pin 32) | Primary battery input | Accepts 4.5–27 V; protected per ISO 7637-3; powers internal regulators and oscillator independently of V1/V2. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated CAN + LIN transceivers | Eliminates discrete transceiver components; enables single-chip ECU networking with bus-level wake-up and fault reporting. |
| Independent V1/V2 regulation | Prevents CAN bus disruption during MCU supply faults; allows V2 to remain active while V1 is disabled in Sleep mode. |
| Programmable watchdog with window mode | Enables deterministic failure recovery: resets occur only if trigger falls outside defined time window - critical for ASIL-B systems. |
| Thermal protection with limp home | Triggers LIMP output LOW and RSTN LOW upon chip overtemperature; releases only after hysteresis-based cooldown. |
| Low-power standby/sleep modes | Standby draws current while maintaining V1 and wake detection; Sleep cuts V1/V2 and transceivers - reducing quiescent current to µA range. |
Applications
| Body Control Module (BCM) | Engine Control Unit (ECU) |
|---|---|
|
Use Scenario: Centralized power and communication hub managing door locks, lighting, and climate sensors via LIN sub-bus while connecting to main CAN backbone. IC Role / Device Role / Timing Role: UJA1075TW/3V3,118 provides regulated 3.3 V power to MCU, interfaces LIN slaves (e.g., mirror controls), and relays CAN messages between gateway and peripherals. Use Value: Reduces BOM count by integrating transceivers and regulators; LIN low-slope mode minimizes radiated emissions in cabin-sensitive zones. |
Use Scenario: Power management and bus interface for engine sensor acquisition and actuator control under harsh thermal/voltage conditions (e.g., cranking, load dump). IC Role / Device Role / Timing Role: UJA1075TW/3V3,118 supplies stable 3.3 V to engine MCU, monitors CAN bus for diagnostic commands, and asserts LIMP output during thermal runaway. Use Value: Operates down to 4.5 V VBAT during cranking; ±58 V short-circuit proof CAN pins prevent damage from inductive spikes. |
| Transmission Control Unit (TCU) | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
|
Use Scenario: Coordinating gear shift logic, solenoid drivers, and vehicle speed data across CAN and LIN networks in automatic transmission assemblies. IC Role / Device Role / Timing Role: UJA1075TW/3V3,118 delivers 3.3 V to TCU MCU, handles CAN diagnostics, and uses WAKE1/WAKE2 to detect gear selector position changes. Use Value: Dual wake-up inputs enable fast response to mechanical inputs without MCU polling; V2 isolation ensures CAN remains functional during V1 transient dips. |
Use Scenario: Aggregating radar, camera, and ultrasonic sensor data in distributed ADAS nodes requiring robust EMC and fail-safe signaling. IC Role / Device Role / Timing Role: UJA1075TW/3V3,118 powers vision processor, routes CAN alerts to central domain controller, and triggers LIMP to disable actuators during sensor fault. Use Value: ±8 kV HBM ESD on CAN/LIN pins protects against assembly-line discharge; SPLIT pin improves signal integrity on long sensor harnesses. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1043TK/3V3/1 | Single high-speed CAN transceiver only; no LIN, no regulators, no watchdog; 3.3 V I/O compatible but requires external power management. | Used where CAN-only interface suffices and MCU power is supplied separately; lacks integrated diagnostics and limp home capability. | Select when cost-sensitive designs require minimal CAN physical layer without SBC-level system control. |
| UJA1169ATW/3V3/1 | Successor SBC with enhanced CAN FD support, higher V1 current (350 mA), improved watchdog (window + timeout + early-warning), and extended temperature range (−40 °C to +150 °C). | Targets next-gen ECUs needing CAN FD bandwidth, higher power delivery, and extended thermal resilience beyond UJA1075TW/3V3,118's −40 °C to +125 °C rating. | Choose for new designs requiring future-proofing, higher current, or CAN FD - not drop-in compatible due to pinout and register differences. |
Compared with TJA1043TK/3V3/1, UJA1075TW/3V3,118 integrates full ECU subsystems (power, CAN, LIN, watchdog) reducing board space and validation effort; versus UJA1169ATW/3V3/1, it offers proven automotive qualification at lower complexity but lacks CAN FD and extended thermal margin.
Availability
UJA1075TW/3V3,118 is available at Aetrix Electronics and suitable for automotive body control modules, engine control units, and transmission control units requiring stable component supply across production lifecycles and environmental extremes.
Supply support for UJA1075TW/3V3,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade mixed-signal ICs.
The UJA1075TW/3V3,118 belongs to NXP's System Basis Chip product line, engineered specifically for automotive ECU consolidation - combining power regulation, CAN/LIN communication, and safety-critical supervision in a single AEC-Q100 qualified device.
FAQ
What is the V1 output voltage tolerance of the UJA1075TW/3V3,118 in LIN master applications?
The UJA1075TW/3V3,118 specifies ±2 % output voltage tolerance for its 3.3 V V1 regulator when used in LIN master applications, ensuring stable timing for LIN baud rate generation. This tolerance is tighter than the ±3 % specified for LIN slave use cases, reflecting stricter requirements for master node clock accuracy.
Does the UJA1075TW/3V3,118 support CAN FD communication?
No, the UJA1075TW/3V3,118 does not support CAN FD. It integrates a high-speed CAN transceiver compliant only with ISO 11898-2 and ISO 11898-5 for classical CAN (up to 1 Mbit/s). CAN FD capability was introduced in later-generation SBCs such as the UJA1169 series.
How does the watchdog in the UJA1075TW/3V3,118 behave in Window mode?
In Window mode, the UJA1075TW/3V3,118 watchdog requires a trigger event within a defined time window - not too early (first half) and not too late (after timeout). Triggering outside this window causes an immediate system reset. The default window period is 128 ms, programmable via NWP bits in the WD_and_Status register.
Can the UJA1075TW/3V3,118 operate during automotive cranking conditions?
Yes, the UJA1075TW/3V3,118 is designed to operate during cranking: its V1 regulator functions down to 4.5 V VBAT (per ISO 7637 pulse 4/4b), and V2 operates down to 5.5 V. Both regulators maintain stable output and retain undervoltage detection functionality throughout these low-voltage transients.
What is the purpose of the SPLIT pin on the UJA1075TW/3V3,118?
Pin 24 (SPLIT) on the UJA1075TW/3V3,118 connects to an external 4.7 nF capacitor to stabilize the recessive common-mode voltage on the CAN bus. This reduces ringing caused by bus reflections, improving signal integrity and EMC performance - especially in longer or unterminated CAN networks.
UJA1075TW/3V3,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- CAN, LIN
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1075TW/3V3,118 FAQ
1.How can I place an order for UJA1075TW/3V3,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1075TW/3V3,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1075TW/3V3,118 reliable?
The price and inventory of UJA1075TW/3V3,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1075TW/3V3,118 is usually 5 days.
3.What payment methods are accepted for UJA1075TW/3V3,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1075TW/3V3,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1075TW/3V3,118?
UJA1075TW/3V3,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1075TW/3V3,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1075TW/3V3,118?
For technical support, including UJA1075TW/3V3,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1075TW/3V3,118 requirements.
6.How does Aetrix verify that UJA1075TW/3V3,118 is sourced from the original manufacturer or authorized distributors?
All UJA1075TW/3V3,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1075TW/3V3,118 meets industry standards.
7.What is the process for return or replacement of UJA1075TW/3V3,118?
All UJA1075TW/3V3,118 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1075TW/3V3,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1075TW/3V3,118 part is unused and in its original packaging.
Return procedure for UJA1075TW/3V3,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UJA1075TW/3V3,118 Tags

-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments

-
MD0100N8-G
Microchip Technology

-
PCA9548APW,118
NXP Semiconductors

-
PCA9540BDP,118
NXP Semiconductors

-
PCA9548APWR
Texas Instruments

-
PCA9546APW,118
NXP Semiconductors

-
PTN3360DBS,518
NXP Semiconductors

-
PCA9546ABS,118
NXP Semiconductors

-
PCA9518PWR
Texas Instruments

-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

