NXP Semiconductors UJA1075TW/3V3/WD:1

Overview

UJA1075TW/3V3/WD from NXP Semiconductors is a core System Basis Chip (SBC) integrating a high-speed CAN transceiver (ISO 11898-2/5 compliant), LIN 2.1 transceiver (SAE J2602 compliant), 3.3 V/250 mA microcontroller voltage regulator, dedicated 5 V CAN transceiver regulator, SPI interface, and advanced watchdog with window/timeout modes - deployed in automotive Electronic Control Units for centralized power, communication, and safety management.

For engineers reviewing the UJA1075TW/3V3/WD datasheet, UJA1075TW/3V3/WD pinout, UJA1075TW/3V3/WD application, or UJA1075TW/3V3/WD equivalent, key selection considerations include its 3.3 V V1 regulator accuracy (±2 % for LIN master), HTSSOP32 package thermal performance, wake-up source detection (CAN/LIN/WAKE1/WAKE2), limp home output behavior during overtemperature, and SPI-configurable mode control (Standby/Normal/Sleep).

Technical Context

The UJA1075TW/3V3/WD implements a state-machine-based system controller managing five operational modes (Off, Standby, Normal, Sleep, Overtemp) with deterministic transitions triggered by VBAT thresholds, wake events, or register writes. Its dual-regulator architecture isolates V1 (3.3 V for MCU/peripherals) from V2 (5 V for CAN transceiver), enabling independent undervoltage monitoring (90 % V1 reset threshold, 90 % V2 warning) and cranking resilience (V1 functional down to 4.5 V, V2 down to 5.5 V per ISO 7637).

Communication uses full-duplex SPI (16-bit, SCSN/SCK/SDI/SDO) for register access (WD_and_Status, Mode_Control, Int_Control), supporting read-only reads and interrupt-driven diagnostics. The integrated watchdog operates from an on-chip oscillator, supports programmable periods (128 ms default), and enforces safe reset behavior in Window mode - including immediate reset on overflow or early trigger, and automatic re-enable after interrupt-induced wake-up.

Key Specifications

Pinout & Package

UJA1075TW/3V3/WD is housed in a 32-pin HTSSOP package (SOT549-1) with 6.1 mm body width, 0.65 mm lead pitch, and exposed die pad for enhanced thermal conduction to the PCB. The die pad is electrically isolated and may be left floating or connected to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar SBC applications.

Compared with TJA1043TK/3, UJA1075TW/3V3/WD reduces system complexity by integrating LIN, dual regulators, and watchdog; compared with UJA1076TW/3V3/WD, it lacks EEPROM but offers identical real-time control and diagnostic capabilities at lower cost.

Availability

UJA1075TW/3V3/WD is available at Aetrix Electronics and suitable for automotive body control modules, engine control units, transmission control modules, and ADAS sensor hubs requiring stable component supply, long-term lifecycle support, and AEC-Q100 qualified performance.

Supply support for UJA1075TW/3V3/WD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with leadership in CAN, LIN, and automotive power management ICs.

The UJA1075TW/3V3/WD belongs to NXP's System Basis Chip product line, designed specifically for automotive ECU consolidation - integrating communication, power, and safety functions into a single AEC-Q100 qualified device to simplify design and improve reliability.

FAQ

What is the nominal output voltage and accuracy of the main regulator in UJA1075TW/3V3/WD?

The UJA1075TW/3V3/WD features a 3.3 V main regulator (V1) with ±2 % accuracy for LIN master applications and ±3 % for LIN slave applications. This precision ensures reliable MCU operation and accurate LIN timing, and the regulator delivers up to 250 mA while supporting external PNP extension for higher current demands and improved thermal distribution across the PCB.

How does the watchdog function in UJA1075TW/3V3/WD differ from basic timeout watchdogs?

The UJA1075TW/3V3/WD implements a programmable watchdog with Window, Timeout, and Off modes - clocked by an independent on-chip oscillator. In Window mode, it requires triggers within a defined time window (not just before timeout), preventing premature or late resets. It also supports automatic re-enable after interrupt wake-up and can be disabled via WDOFF pin or WMC bit, offering greater flexibility than fixed timeout watchdogs.

Can UJA1075TW/3V3/WD operate during automotive cranking conditions?

Yes, UJA1075TW/3V3/WD is designed for automotive cranking: V1 remains functional down to 4.5 V VBAT (per ISO 7637 pulse 4/4b and ISO 16750-2), and V2 operates down to 5.5 V. Its undervoltage detection thresholds (90 % of nominal) and robust protection (±58 V bus short-circuit, ±8 kV HBM ESD) ensure reliable startup and sustained operation during battery voltage sag.

What is the role of the SPLIT pin on UJA1075TW/3V3/WD and how is it used?

The SPLIT pin (Pin 24) on UJA1075TW/3V3/WD provides a common-mode stabilization signal for the CAN bus, connecting to a split termination resistor (e.g., two 60 Ω resistors to Vref). This configuration suppresses recessive-level bus ringing and improves signal integrity - especially critical in high-noise automotive environments - without requiring external active components.

Does UJA1075TW/3V3/WD support both CAN and LIN wake-up in Sleep mode?

Yes, UJA1075TW/3V3/WD supports CAN and LIN wake-up in Sleep mode when STBCC = 1 and STBCL = 1 (via Int_Control register). In this configuration, the transceivers remain in Lowpower mode with bus wake-up detection enabled, allowing the SBC to transition to Standby and assert RSTN upon valid bus activity - all while maintaining ultra-low sleep current (<100 µA).