NXP Semiconductors UJA1075TW/5V0,118
- Part No.:
- UJA1075TW/5V0,118
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1075TW/5V0,118.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1075TW/5V0,118 from NXP Semiconductors is a high-speed CAN/LIN core System Basis Chip (SBC) integrating a 5 V microcontroller voltage regulator (250 mA), ISO 11898-2/5-compliant CAN transceiver, LIN 2.1 transceiver, SPI interface, dual wake-up inputs, and limp home output - designed for automotive ECU power and communication management in engine control, body electronics, and chassis modules.
For engineers reviewing the UJA1075TW/5V0,118 datasheet, UJA1075TW/5V0,118 pinout, UJA1075TW/5V0,118 application, or UJA1075TW/5V0,118 equivalent, this page delivers verified functional partitioning, automotive-grade EMC/ESD specs (±8 kV HBM), thermal-aware regulator architecture, and precise mode-control behavior across Standby/Normal/Sleep states.
Technical Context
The UJA1075TW/5V0,118 implements dual independent voltage regulation: V1 delivers 5 V ±3 % at up to 250 mA for the MCU and peripherals, with external PNP extension support and 90 % undervoltage warning; V2 supplies 5 V to the integrated CAN transceiver, switchable off and stable down to 5.5 V battery input during cranking (ISO 7637-4).
Its system controller manages four operational modes (Off, Standby, Normal, Sleep) via the Mode_Control register (MC bits), with wake-up detection on CAN, LIN, or local WAKE1/WAKE2 pins, and includes a programmable watchdog with Window/Timeout/Off modes clocked by an on-chip oscillator - all communicated over a full-duplex 16-bit SPI interface with read-only register access capability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Interface | ISO 11898-2 and ISO 11898-5 compliant high-speed transceiver; supports bus wake-up and SPLIT pin for recessive level stabilization |
| LIN Interface | LIN 2.1 and SAE J2602 compliant; downward compatible with LIN 2.0/1.3; low-slope mode (10.4 kbit/s) for optimized EMC |
| V1 Regulator Output | 5 V ±3 % accuracy (LIN slave); 250 mA max; undervoltage warning at 90 % nominal; supports external PNP transistor for thermal distribution |
| V2 Regulator Output | 5 V dedicated supply for internal CAN transceiver; switchable off; undervoltage warning at 90 % nominal; operates down to 5.5 V VBAT |
| Watchdog | Programmable Window/Timeout/Off modes; default period 128 ms; triggered by WD_and_Status register write; independent on-chip oscillator clock source |
| SPI Interface | 16-bit full-duplex; SCSN/SDI/SCK/SDO signals; register read-back without modification; supports multi-slave configuration |
| Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm body; 0.65 mm pitch; exposed die pad for PCB thermal dissipation |
Pinout & Package
HTSSOP32 package (SOT549-1) with 32 leads, 6.1 mm body width, 0.65 mm lead pitch, and exposed die pad thermally connected to PCB ground or left floating per design requirements.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BAT (32) | Battery supply input | Primary power source for SBC; supports operation down to 4.5 V during cranking (ISO 16750-2) |
| V1 (4) | Main MCU supply output | 5 V regulated output; ±3 % accuracy; 250 mA max; enables external PNP extension via VEXCTRL/VEXCC |
| V2 (20) | CAN transceiver supply | Dedicated 5 V regulator; independent of V1; can be disabled to reduce quiescent current in Standby |
| RSTN (6) | Bidirectional reset I/O | Drives LOW during power-on, watchdog overflow, or overtemperature; configurable reset pulse length |
| INTN (7) | Interrupt output | Open-drain signal indicating V1/V2 undervoltage, CAN/LIN/local wake-up, cyclic, or power-on events |
| WAKE1 (18), WAKE2 (19) | Local wake-up inputs | Configurable sampling (16 ms or 64 ms) via WBIAS; support wake-up source detection and interrupt generation |
| LIMP (17) | Limp home control output | Active-low signal activated during overtemperature or critical fault; enables fail-safe hardware activation |
| SPI Signals (SDI/SDO/SCK/SCSN) | Microcontroller interface | Full-duplex 16-bit SPI for configuration, status reporting, and diagnostics; supports read-only register access |
Key Features
| Feature | Design Value |
|---|---|
| Automotive-grade ESD protection | ±8 kV HBM and ±6 kV IEC 61000-4-2 on CAN/LIN/wake pins - ensures robustness in harsh vehicle environments |
| Short-circuit tolerant bus pins | ±58 V short-circuit proof CANH/CANL/LIN pins - eliminates need for external TVS in many ECU designs |
| Advanced low-power architecture | Standby current < 100 µA and Sleep current < 30 µA with full wake-up capability - meets OEM sleep current targets |
| Integrated LIN termination diode | DLIN pin hosts internal diode for LIN bus termination - reduces BOM count and improves layout reliability |
| Overtemperature shutdown with hysteresis | OTP activation at Tth(act)otp; release at Tth(rel)otp with hysteresis - prevents thermal runaway and enables safe recovery |
| Remote flash programming support | Enables firmware updates via CAN bus without physical access - critical for OTA and service depot reprogramming |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
|
Use Scenario: Centralized power and communication management for diesel/gasoline engine controllers requiring CAN-based sensor/actuator networking and LIN-connected auxiliary devices. IC Role / Device Role / Timing Role: Core SBC providing controlled MCU startup, CAN/LIN bridging, V1/V2 regulation, and limp-home fail-safe response during overtemperature or undervoltage faults. Use Value: Eliminates discrete CAN/LIN transceivers, regulators, and watchdog ICs - reducing board area by >40 % and enabling ASIL-B–compliant ECU designs. |
Use Scenario: Power and bus interface for door module, lighting, or seat control units where low standby current and LIN sub-bus coordination are mandatory. IC Role / Device Role / Timing Role: Manages MCU supply (V1), LIN master/slave communication, local wake-up from door switches, and failsafe LIMP activation during power loss. Use Value: Achieves < 30 µA Sleep current with full wake-up capability - directly meeting OEM BCM quiescent current specifications (e.g., Ford WSD-1234, GM GP-101). |
| Chassis Control System | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
|
Use Scenario: ECU for brake-by-wire or steering control where functional safety, EMC immunity, and deterministic wake-up latency are critical. IC Role / Device Role / Timing Role: Provides ISO 11898-2 CAN physical layer, 5 V V1 supply with 90 % undervoltage warning, and SPI-configurable watchdog window timing for ASIL-C monitoring. Use Value: Delivers ±58 V bus fault tolerance and ±8 kV HBM ESD - exceeding ISO 11452-2/IEC 61000-4-2 requirements for chassis domain ECUs. |
Use Scenario: Central hub aggregating radar, camera, and ultrasonic sensors via CAN backbone and LIN-peripheral interfaces in ADAS domain controllers. IC Role / Device Role / Timing Role: Supplies 5 V to host MCU, routes CAN traffic to sensor nodes, enables LIN wake-up for low-power sensor polling, and reports faults via SPI-interrupts. Use Value: Integrates CAN/LIN transceivers with independent regulators - avoids cross-talk between high-noise CAN and sensitive analog sensor supplies. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar System Basis Chip applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1043TK/3V3/1 | 3.3 V V1 regulator only; no LIN transceiver; single CAN interface; no SPI or watchdog | Targeted at CAN-only gateways or simple sensor nodes - lacks LIN, SPI, and advanced power management | Select when LIN integration and MCU-level diagnostics are unnecessary and 3.3 V MCU supply suffices |
| UJA1169ATW/5V0/1 | Includes embedded 32-bit ARM Cortex-M0+ MCU; adds CAN FD support; higher integration but larger footprint | Designed for software-defined ECUs requiring firmware execution - not a drop-in replacement due to MCU presence and pinout change | Choose when migrating from discrete SBC + MCU to integrated SoC architecture with CAN FD and OTA update capability |
Compared with TJA1043TK/3V3/1, UJA1075TW/5V0,118 provides full LIN+CAN coexistence and SPI-based diagnostics; versus UJA1169ATW/5V0/1, it offers lower BOM cost and smaller HTSSOP32 footprint for legacy CAN/LIN ECU upgrades without MCU redesign.
Availability
UJA1075TW/5V0,118 is available at Aetrix Electronics and suitable for automotive engine control, body electronics, and chassis systems requiring stable component supply, long-term lifecycle assurance, and AEC-Q100 Grade 1 qualification compliance.
Supply support for UJA1075TW/5V0,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade mixed-signal ICs and functional safety certification.
The UJA1075TW/5V0,118 belongs to NXP's System Basis Chip product line - engineered specifically for automotive ECU consolidation, delivering integrated power management, CAN/LIN networking, and fail-safe control in a single HTSSOP32 package.
FAQ
What is the nominal output voltage and accuracy of the V1 regulator in UJA1075TW/5V0,118?
The UJA1075TW/5V0,118 features a 5 V V1 regulator with ±3 % output voltage accuracy specified for LIN slave applications. This tolerance ensures reliable operation of common automotive microcontrollers while supporting external PNP extension for higher current loads. The regulator includes undervoltage warning at 90 % of nominal output and configurable reset thresholds at either 90 % or 70 % of nominal voltage.
Does UJA1075TW/5V0,118 include a watchdog timer, and how is it configured?
Yes, UJA1075TW/5V0,118 includes a programmable watchdog with Window, Timeout, and Off modes. It is clocked by an independent on-chip oscillator and configured via the WD_and_Status register (bits WMC and NWP). The default watchdog period is 128 ms, and trigger events occur on any write to that register. Pin WDOFF allows hardware deactivation, and the watchdog automatically re-enables after interrupts in Standby mode.
How does the UJA1075TW/5V0,118 support low-power operation in automotive standby and sleep modes?
The UJA1075TW/5V0,118 achieves ultra-low quiescent current: < 100 µA in Standby mode (V1 active) and < 30 µA in Sleep mode (V1/V2 off). Wake-up is supported via CAN, LIN, or local WAKE1/WAKE2 inputs with configurable sampling intervals (16 ms or 64 ms). The SBC transitions deterministically between Off, Standby, Normal, and Sleep modes using the Mode_Control register (MC bits), ensuring compliance with OEM sleep current targets.
What automotive standards does UJA1075TW/5V0,118 comply with for EMC and electrical robustness?
UJA1075TW/5V0,118 complies with ISO 11898-2 and ISO 11898-5 for high-speed CAN, LIN 2.1 and SAE J2602 for LIN, and includes ±8 kV HBM and ±6 kV IEC 61000-4-2 ESD protection on CAN/LIN/wake pins. Its bus pins are ±58 V short-circuit proof, and it withstands ISO 7637-3 transients and ISO 16750-2 cranking profiles (VBAT down to 4.5 V for V1, 5.5 V for V2).
Can UJA1075TW/5V0,118 be used with both 3.3 V and 5 V microcontrollers?
No - the UJA1075TW/5V0,118 variant is specifically configured with a 5 V V1 regulator output. For 3.3 V microcontrollers, the pin-compatible UJA1075TW/3V3,118 version must be selected. Both variants share identical functionality, pinout, and package (HTSSOP32), differing only in V1 output voltage and associated accuracy spec (±2 % for LIN master in 3.3 V version).
UJA1075TW/5V0,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- CAN, LIN
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1075TW/5V0,118 FAQ
1.How can I place an order for UJA1075TW/5V0,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1075TW/5V0,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1075TW/5V0,118 reliable?
The price and inventory of UJA1075TW/5V0,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1075TW/5V0,118 is usually 5 days.
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Once your UJA1075TW/5V0,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1075TW/5V0,118?
For technical support, including UJA1075TW/5V0,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1075TW/5V0,118 requirements.
6.How does Aetrix verify that UJA1075TW/5V0,118 is sourced from the original manufacturer or authorized distributors?
All UJA1075TW/5V0,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1075TW/5V0,118 meets industry standards.
7.What is the process for return or replacement of UJA1075TW/5V0,118?
All UJA1075TW/5V0,118 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1075TW/5V0,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1075TW/5V0,118 part is unused and in its original packaging.
Return procedure for UJA1075TW/5V0,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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