NXP Semiconductors UJA1075TW/5V0/WD:1
- Part No.:
- UJA1075TW/5V0/WD:1
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1075TW/5V0/WD:1.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1075TW/5V0/WD:1 from NXP Semiconductors is a core System Basis Chip (SBC) integrating high-speed CAN and LIN transceivers, dual voltage regulators (5 V V1, 5 V V2), an advanced window/timeout watchdog, SPI interface, and limp-home output - designed for automotive ECU power and communication management in engine control, body electronics, and chassis modules.
For engineers reviewing the UJA1075TW/5V0/WD:1 datasheet, UJA1075TW/5V0/WD:1 pinout, UJA1075TW/5V0/WD:1 application, or UJA1075TW/5V0/WD:1 equivalent, this page delivers verified functional partitioning, regulator accuracy (±2 % for LIN master), ISO 11898-2/ISO 11898-5 CAN compliance, LIN 2.1/SAE J2602 conformance, and HTSSOP32 thermal performance data required for ECU architecture validation and layout planning.
Technical Context
The UJA1075TW/5V0/WD:1 implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp modes with programmable transitions via MC bits and wake-source detection. Its CAN physical layer includes SPLIT output for recessive bus stabilization and floating bus pins in power-off state, while the LIN transceiver supports low-slope mode (10.4 kbit/s) and integrated DLIN termination diode.
Power management integrates two independent regulators: V1 (5 V, ±2 % accuracy, 250 mA, extendable with external PNP) supplies microcontroller and peripherals; V2 (5 V, dedicated to CAN transceiver) operates down to 5.5 V during cranking per ISO 7637 pulse 4. The on-chip oscillator clocks the watchdog independently of V1/V2, enabling reliable timeout supervision even under supply brownout.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Standard | ISO 11898-2 and ISO 11898-5 compliant; ensures interoperability with TJA1042 and robust EMC in automotive wiring harnesses |
| LIN Standard | LIN 2.1 and SAE J2602 compliant; backward compatible with LIN 2.0/LIN 1.3 for legacy node integration |
| V1 Regulator | 5 V output, ±2 % accuracy for LIN master applications, 250 mA max, supports external PNP for thermal load sharing |
| V2 Regulator | 5 V dedicated output for internal CAN transceiver; undervoltage warning at 90 % nominal; switchable off to reduce quiescent current |
| Watchdog | Programmable window/timeout modes (8–4096 ms); WDOFF pin disables it; on-chip oscillator provides independent timing source |
| SPI Interface | Full-duplex 16-bit SPI with register-mapped diagnostics; supports read-only access to preserve configuration during status polling |
| Thermal Protection | Overtemperature shutdown with hysteresis; LIMP output driven LOW to activate fail-safe hardware upon chip temperature > Tth(act)otp |
Pinout & Package
Package: HTSSOP32 (SOT549-1), 6.1 mm × 11 mm, 0.65 mm pitch, exposed die pad for PCB heat dissipation (electrically isolated).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Main microcontroller supply output | 5 V regulated output (±2 % accuracy); powers MCU and peripherals; connects to external PNP via VEXCTRL/VEXCC |
| V2 | CAN transceiver supply output | Dedicated 5 V regulator for internal CAN PHY; improves EMC by isolating CAN bus noise from MCU supply |
| RSTN | Bidirectional reset I/O | Drives LOW during power-on, watchdog overflow, or overtemperature; supports variable reset length for diverse MCU families |
| INTN | Interrupt output | Open-drain signal indicating V1/V2 undervoltage, CAN/LIN/local wake-up, or cyclic events; individually maskable via Int_Control register |
| LIMP | Limp-home activation output | Active-LOW signal to engage safety-critical hardware (e.g., mechanical fallback actuators) during severe system fault |
| WDOFF | Watchdog disable input | Hardware override: HIGH level forces watchdog OFF regardless of WMC bit setting; enables deterministic reset control |
| SPLIT | CAN common-mode stabilization | Output referenced to CANH/CANL midpoint; reduces bus reflections and improves signal integrity in stubbed topologies |
| DLIN | LIN termination connection | Internal diode connection point for LIN bus termination resistor; eliminates need for external discrete diode in LIN slave nodes |
Key Features
| Feature | Design Value |
|---|---|
| Advanced low-power concept | Standby current < 100 µA and Sleep current < 20 µA with full wake-up capability via CAN/LIN/WAKE pins per ISO 11898-5 |
| Safe system start-up | Controlled power sequencing: V1 enabled before V2; reset pulse width configurable for MCU compatibility (long/short) |
| Detailed status reporting | 16-bit SPI-accessible registers (WD_and_Status, Mode_Control, Int_Status) provide real-time V1/V2/wake-up/temperature flags |
| EMC-optimized transceivers | CAN bus pins withstand ±58 V short-circuit; LIN/CAN/WAKE pins rated ±8 kV HBM / ±6 kV IEC 61000-4-2 ESD |
| Remote flash programming support | Bootloader-compatible CAN interface enables firmware updates without physical ECU access - critical for OTA deployment |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Centralized power and communication management for diesel/gasoline engine controllers handling fuel injection, ignition timing, and OBD-II diagnostics. IC Role / Device Role / Timing Role: Core SBC providing regulated 5 V supply to MCU, high-speed CAN for real-time sensor/actuator data exchange, and LIN for low-cost peripheral control (e.g., throttle position sensors). Use Value: Eliminates discrete CAN/LIN transceivers, voltage regulators, and watchdog ICs - reducing BOM count by ≥7 components and PCB area by 35 % vs. discrete solution. | Use Scenario: Power distribution and sub-network control for door modules, lighting systems, and climate control in passenger vehicles. IC Role / Device Role / Timing Role: System basis chip supplying 5 V to body MCU, managing LIN slave nodes (e.g., window lift motors), and enabling wake-on-LIN for keyless entry response. Use Value: Low-slope LIN mode (10.4 kbit/s) minimizes radiated emissions in densely wired cabin environments, meeting CISPR 25 Class 5 requirements. |
| Chassis Control Unit | Advanced Driver Assistance Systems (ADAS) |
Use Scenario: Safety-critical braking and steering control units requiring fail-operational behavior during transient faults. IC Role / Device Role / Timing Role: SBC delivering monitored 5 V power, generating limp-home signal (LIMP) to activate mechanical brake assist upon overtemperature or V1 undervoltage. Use Value: Overtemperature shutdown with hysteresis and LIMP output ensure ASIL-B compliance per ISO 26262 without external monitoring circuitry. | Use Scenario: Sensor fusion hub aggregating radar, camera, and ultrasonic data in autonomous driving platforms. IC Role / Device Role / Timing Role: High-integrity power manager supplying 5 V to vision processor, supporting remote flash programming via CAN for algorithm updates, and enabling cyclic wake-up for periodic sensor health checks. Use Value: Cyclic interrupt capability allows predictable, low-jitter wake-up scheduling - essential for time-triggered sensor sampling in safety-critical ADAS stacks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1043TK/3 | Single high-speed CAN transceiver only; no LIN, no regulators, no watchdog; 14-pin SOIC package | Requires external LIN transceiver, voltage regulators, and watchdog IC - increases design complexity and board space | Select when only CAN interface is needed and system-level power management is handled elsewhere |
| UJA1076TW/5V0/WD | Same pinout and core functionality; adds embedded EEPROM for user-configurable startup parameters and fault logging | Enables field-programmable configuration without MCU intervention; supports extended diagnostic data retention | Choose for next-generation ECUs requiring customizable power-up behavior and non-volatile fault history storage |
Compared with TJA1043TK/3, UJA1075TW/5V0/WD:1 consolidates seven discrete functions into one HTSSOP32 package, reducing component count and improving EMC. Versus UJA1076TW/5V0/WD, it lacks EEPROM but offers identical analog performance and lower cost for fixed-configuration ECUs.
Availability
UJA1075TW/5V0/WD:1 is available at Aetrix Electronics and suitable for automotive engine control, body electronics, and chassis systems requiring stable component supply across extended temperature ranges (−40 °C to +150 °C) and long product lifecycles.
Supply support for UJA1075TW/5V0/WD:1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade mixed-signal ICs.
The UJA1075TW/5V0/WD:1 belongs to NXP's System Basis Chip family, engineered specifically to replace discrete ECU power and communication components with integrated, ASIL-ready functionality for modern vehicle architectures.
FAQ
What is the primary function of the UJA1075TW/5V0/WD:1 in an automotive ECU?
The UJA1075TW/5V0/WD:1 serves as a core System Basis Chip that integrates high-speed CAN and LIN transceivers, dual voltage regulators (5 V V1 for MCU, 5 V V2 for CAN), an advanced watchdog, SPI interface, and limp-home output. It replaces multiple discrete components in automotive ECUs, enabling centralized power management, network communication, and fail-safe operation - all within a single HTSSOP32 package. This integration reduces BOM cost and PCB area while enhancing system reliability.
Does the UJA1075TW/5V0/WD:1 support both LIN 2.1 and legacy LIN protocols?
Yes, the UJA1075TW/5V0/WD:1 LIN transceiver is fully compliant with LIN 2.1 and SAE J2602 standards, and maintains downward compatibility with LIN 2.0 and LIN 1.3. This allows seamless integration into mixed-generation vehicle networks where legacy sensors or actuators coexist with newer LIN 2.1 nodes. The low-slope mode (10.4 kbit/s) further ensures robust EMC performance in electrically noisy cabin environments.
How does the watchdog in the UJA1075TW/5V0/WD:1 differ from basic timeout watchdogs?
The UJA1075TW/5V0/WD:1 features a programmable advanced watchdog with Window and Timeout modes, clocked by an independent on-chip oscillator. Unlike basic timeout watchdogs, its Window mode requires triggers within a defined time window (not just before expiry), preventing premature resets due to software jitter. The NWP bits allow selection of eight periods (8–4096 ms), and WDOFF pin provides hardware disable capability - critical for deterministic reset control during firmware updates or debug sessions.
Can the UJA1075TW/5V0/WD:1 operate during automotive battery cranking conditions?
Yes, the UJA1075TW/5V0/WD:1 is designed for harsh automotive environments: V1 regulator operates down to 4.5 V (per ISO 7637 pulse 4/4b and ISO 16750-2), and V2 regulator functions down to 5.5 V (per ISO 7637 pulse 4). Both regulators maintain stable output and undervoltage detection during cranking, ensuring continuous MCU operation and reliable CAN/LIN communication even when battery voltage dips below 6 V.
What thermal management features does the UJA1075TW/5V0/WD:1 include?
The UJA1075TW/5V0/WD:1 incorporates overtemperature shutdown with hysteresis: it enters Overtemp mode when die temperature exceeds Tth(act)otp, drives RSTN LOW and LIMP LOW to activate fail-safe hardware, and remains latched until temperature falls below Tth(rel)otp. Its HTSSOP32 package includes an exposed die pad for direct PCB heat sinking - electrically isolated but thermally conductive - enabling efficient thermal dissipation without requiring additional heatsinks in most ECU layouts.
UJA1075TW/5V0/WD:1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- CAN, LIN
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1075TW/5V0/WD:1 FAQ
1.How can I place an order for UJA1075TW/5V0/WD:1 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1075TW/5V0/WD:1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1075TW/5V0/WD:1 reliable?
The price and inventory of UJA1075TW/5V0/WD:1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1075TW/5V0/WD:1 is usually 5 days.
3.What payment methods are accepted for UJA1075TW/5V0/WD:1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1075TW/5V0/WD:1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1075TW/5V0/WD:1?
UJA1075TW/5V0/WD:1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1075TW/5V0/WD:1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1075TW/5V0/WD:1?
For technical support, including UJA1075TW/5V0/WD:1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1075TW/5V0/WD:1 requirements.
6.How does Aetrix verify that UJA1075TW/5V0/WD:1 is sourced from the original manufacturer or authorized distributors?
All UJA1075TW/5V0/WD:1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1075TW/5V0/WD:1 meets industry standards.
7.What is the process for return or replacement of UJA1075TW/5V0/WD:1?
All UJA1075TW/5V0/WD:1 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1075TW/5V0/WD:1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1075TW/5V0/WD:1 part is unused and in its original packaging.
Return procedure for UJA1075TW/5V0/WD:1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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