NXP Semiconductors UJA1076TW/3V3,112
- Part No.:
- UJA1076TW/3V3,112
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1076TW/3V3,112.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1076TW/3V3,112 from NXP Semiconductors is a high-speed CAN core System Basis Chip (SBC) integrating a 3.3 V/250 mA microcontroller regulator, ISO 11898-2/5-compliant CAN transceiver, SPI interface, dual wake-up inputs, limp-home output, and watchdog - designed for automotive ECU power and communication management in engine control, body electronics, and chassis modules.
For engineers reviewing the UJA1076TW/3V3,112 datasheet, UJA1076TW/3V3,112 pinout, UJA1076TW/3V3,112 application, or UJA1076TW/3V3,112 equivalent, this page delivers verified functional architecture, automotive-grade EMC/ESD specs, regulator accuracy, thermal shutdown behavior, and SPI register-level control details essential for ECU start-up sequencing, fail-safe design, and CAN network integration.
Technical Context
The UJA1076TW/3V3,112 implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp modes with deterministic transitions triggered by VBAT thresholds, CAN activity, local wake events, or temperature faults. Its dual-regulator architecture isolates V1 (3.3 V ±2 %) for MCU/peripherals from V2 (5 V) dedicated to the CAN transceiver - enabling independent undervoltage monitoring and bus-level EMC optimization.
SPI communication uses full-duplex 16-bit framing with addressable register map (WD_and_Status, Mode_Control, Int_Control, Int_Status), supporting read-only access and interrupt-driven status reporting. The watchdog operates in Window/Timeout/Off modes with on-chip oscillator timing and configurable NWP periods (8–4096 ms), while limphome activation is controlled via LHC/LHWC bits and asserted as active-low on LIMP during overtemperature or critical failure.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Standard | ISO 11898-2 and ISO 11898-5 compliant high-speed physical layer; interoperable with TJA1042 |
| V1 Regulator Output | 3.3 V ±2 %, 250 mA max; supports external PNP transistor for thermal load sharing |
| V2 Regulator Output | 5 V dedicated supply for internal CAN transceiver; switchable off to reduce quiescent current |
| Watchdog Modes | Window, Timeout, and Off modes; programmable nominal period (128 ms default); independent on-chip oscillator clock source |
| SPI Interface | Full-duplex 16-bit; SCSN/SDI/SCK/SDO signals; register-addressed (A2–A0), read/write and read-only access support |
| Wake-up Inputs | WAKE1 and WAKE2 with selectable 16 ms or 64 ms sampling; WBIAS bias control for external pull-up networks |
| ESD Protection | ±8 kV HBM and ±6 kV IEC 61000-4-2 on CANH/CANL and wake pins; ±58 V short-circuit proof bus pins |
| Thermal Protection | Overtemperature shutdown with hysteresis; LIMP output driven LOW and RSTN forced LOW upon activation |
Pinout & Package
Package: HTSSOP32 (SOT549-1), 6.1 mm × 11 mm, 0.65 mm pitch, exposed die pad for PCB thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 (Pin 4) | Main regulator output | 3.3 V ±2 % supply for MCU and peripherals; enables external PNP extension via VEXCTRL/VEXCC |
| RSTN (Pin 6) | Bidirectional reset | Active-low reset input/output; variable power-on reset length supports diverse MCU timing requirements |
| INTN (Pin 7) | Interrupt output | Open-drain signal indicating V1/V2 undervoltage, CAN/local wake-up, cyclic, or power-on events |
| EN (Pin 8) | Enable output | Drives external safety-critical hardware; HIGH in Normal mode when ENC = 1 |
| SDI/SDO/SCK/SCSN (Pins 9–12) | SPI interface | Full-duplex serial control path for configuration, diagnostics, and status readback |
| TXDC/RXDC (Pins 13–14) | CAN logic interface | Direct connection to MCU CAN controller; decoupled from bus-level CANH/CANL |
| WDOFF (Pin 16) | Watchdog disable | Hardware override: HIGH disables watchdog regardless of WMC setting |
| LIMP (Pin 17) | Limp-home output | Active-low signal activating fail-safe hardware during overtemperature or system fault |
| WAKE1/WAKE2 (Pins 18–19) | Local wake inputs | Configurable edge-sensitive inputs with WBIAS bias control and sampling synchronization |
| V2 (Pin 20) | CAN transceiver supply | Dedicated 5 V regulator output; isolated from V1 to maintain CAN bus EMC integrity |
| CANH/CANL (Pins 21–22) | CAN bus interface | High-speed differential bus terminals; ±58 V short-circuit tolerant; floating when powered off |
| SPLIT (Pin 24) | Bus common-mode stabilization | Output for external split termination resistor to suppress recessive-level ringing |
| WBIAS (Pin 28) | Wake bias control | Drives external transistor to bias WAKE1/WAKE2; sampling time selectable (16 ms or 64 ms) |
| VEXCC/VEXCTRL (Pins 29/31) | External PNP interface | VEXCTRL drives base; VEXCC measures collector current to enable current-threshold-controlled PNP activation |
| BAT (Pin 32) | Battery input | VBAT supply (4.5 V–27 V); supports cranking per ISO 7637-3 and ISO 16750-2 |
Key Features
| Feature | Design Value |
|---|---|
| Integrated CAN ECU functions | Single-package consolidation of transceiver, dual regulators, watchdog, SPI, wake logic, and limp-home - eliminating discrete BOM components and reducing layout complexity |
| Automotive-grade robustness | ±8 kV HBM / ±6 kV IEC 61000-4-2 ESD, ±58 V bus short-circuit tolerance, ISO 7637-3 transient protection, and overtemperature shutdown with LIMP assertion |
| Intelligent power sequencing | Deterministic Off→Standby→Normal→Sleep mode transitions with VBAT threshold detection, wake-source identification, and safe reset generation |
| Scalable 3.3 V regulator | V1 delivers 250 mA at ±2 % accuracy; external PNP extension enables >250 mA operation with distributed thermal dissipation across PCB |
| Fail-safe diagnostic interface | SPI-accessible registers (WD_and_Status, Mode_Control, Int_Status) provide real-time visibility into regulator status, wake sources, interrupt flags, and limp-home activation state |
| Low-power wake architecture | Standby/Sleep modes achieve ultra-low quiescent current; wake detection via CAN bus activity or WAKE1/WAKE2 with configurable sampling and biasing |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Real-time coordination of fuel injection, ignition timing, and emissions control using CAN-connected sensors and actuators under harsh under-hood conditions. IC Role / Device Role / Timing Role: UJA1076TW/3V3,112 serves as the central power and communication hub - regulating 3.3 V for the MCU, powering the CAN transceiver independently, and ensuring safe start-up/reset sequencing during cranking or voltage dips. Use Value: Maintains stable 3.3 V supply down to 4.5 V VBAT (ISO 7637 pulse 4), prevents false resets during engine start, and enables remote flash programming via CAN bus. | Use Scenario: Centralized management of door locks, lighting, HVAC, and window controls in passenger compartments with strict EMC and low-power standby requirements. IC Role / Device Role / Timing Role: UJA1076TW/3V3,112 provides always-on wake capability via WAKE1/WAKE2 and CAN bus, powers MCU in Standby mode, and asserts LIMP output if thermal fault occurs during high-current load switching. Use Value: Achieves <100 µA standby current with full wake-up responsiveness; ±8 kV HBM ESD protection ensures reliability against human touch events. |
| Chassis Control Module | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
Use Scenario: Integration of ABS, ESC, and electronic brake control units requiring deterministic CAN communication, precise voltage regulation, and fail-safe behavior during voltage transients. IC Role / Device Role / Timing Role: UJA1076TW/3V3,112 supplies regulated 3.3 V to safety-critical MCU, monitors V1/V2 undervoltage with interrupt signaling, and triggers limp-home output upon overtemperature or watchdog timeout. Use Value: Dual undervoltage warning/reset thresholds (90 % or 70 %) allow configurable reset sensitivity; EN output controls external safety relays. | Use Scenario: Aggregation and preprocessing of radar, camera, and ultrasonic sensor data before transmission over CAN FD backbone in ADAS domain controllers. IC Role / Device Role / Timing Role: UJA1076TW/3V3,112 delivers clean 3.3 V power to sensor interface MCU, isolates CAN transceiver supply (V2) to minimize noise coupling, and enables cyclic wake-up for periodic sensor polling. Use Value: Dedicated V2 regulator improves CAN bus EMC performance; SPI register access allows runtime diagnostics of sensor supply health and wake event sources. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive CAN SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1043TK/3V3/CM | Single-function high-speed CAN transceiver only; no integrated regulators, watchdog, or SPI interface | Requires external 3.3 V regulator, MCU watchdog, and power management ICs - increasing BOM count and board area | Select when only CAN physical layer functionality is needed and system-level power management is handled separately |
| UJA1075TW/3V3,112 | Omits limp-home output and has reduced wake-up pin count (WAKE1 only); identical V1/V2 regulators, CAN compliance, and SPI register set | Not suitable for systems requiring dual-wake inputs or hardware-level limp-home activation during thermal faults | Choose for cost-optimized ECUs where limp-home is implemented in software or external logic, and single wake input suffices |
Compared with TJA1043TK/3V3/CM, UJA1076TW/3V3,112 reduces component count by integrating power, communication, and safety functions; versus UJA1075TW/3V3,112, it adds critical limp-home and dual-wake capability for higher ASIL-ready designs without changing footprint or regulator specs.
Availability
UJA1076TW/3V3,112 is available at Aetrix Electronics and suitable for automotive engine control, body electronics, chassis modules, and ADAS sensor hubs requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant sourcing.
Supply support for UJA1076TW/3V3,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in CAN protocol stacks, power management, and functional safety.
The UJA1076TW/3V3,112 belongs to NXP's System Basis Chip product line, engineered specifically for automotive Electronic Control Units to consolidate power regulation, high-speed CAN communication, and fail-safe monitoring in a single AEC-Q100-qualified device.
FAQ
What is the nominal output voltage and accuracy of the main regulator in UJA1076TW/3V3,112?
The UJA1076TW/3V3,112 features a 3.3 V main regulator (V1) with ±2 % output voltage accuracy across temperature and load conditions. This precision enables reliable operation of automotive-grade microcontrollers and peripheral circuitry without requiring external trimming or compensation circuits. The regulator delivers up to 250 mA and supports external PNP transistor extension for higher current demands.
Does UJA1076TW/3V3,112 include an integrated watchdog timer, and what modes does it support?
Yes, UJA1076TW/3V3,112 includes an integrated watchdog timer with three operational modes: Window, Timeout, and Off. It uses an on-chip oscillator for timing independence from V1/V2 supplies. The nominal period is programmable from 8 ms to 4096 ms via the NWP bits in the WD_and_Status register, with 128 ms as the default. Watchdog behavior is configurable per operating mode and can be disabled via WDOFF pin or WMC bit.
How does the UJA1076TW/3V3,112 handle wake-up events from the CAN bus and local inputs?
The UJA1076TW/3V3,112 supports wake-up via CAN bus activity (RXDC signal) and two dedicated local inputs (WAKE1 and WAKE2). Wake sources are individually configurable for edge sensitivity (rising/falling/both) and sampling timing (16 ms or 64 ms) via the Int_Control register. Status is reported in real time through WLS1/WLS2 bits in the WD_and_Status register and wake interrupt flags in the Int_Status register.
What is the purpose and behavior of the LIMP output pin on UJA1076TW/3V3,112?
The LIMP output pin on UJA1076TW/3V3,112 is an active-low signal used to activate application-specific 'limp home' hardware during serious system malfunctions such as overtemperature or watchdog timeout. It is controlled by the LHC bit in the Mode_Control register and automatically asserted LOW when overtemperature protection activates. The limp-home function remains active until explicitly cleared by firmware or power cycle.
Can UJA1076TW/3V3,112 operate during automotive battery cranking conditions, and what is its minimum VBAT specification?
Yes, UJA1076TW/3V3,112 is designed to operate during cranking events per ISO 7637-3 and ISO 16750-2 standards. Its V1 regulator maintains stable 3.3 V output down to a minimum VBAT of 4.5 V, and V2 regulator operates down to 5.5 V. This ensures uninterrupted MCU and CAN transceiver functionality during engine start, preventing unintended resets or communication loss in demanding automotive environments.
UJA1076TW/3V3,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- SPI Serial
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1076TW/3V3,112 FAQ
1.How can I place an order for UJA1076TW/3V3,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1076TW/3V3,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of UJA1076TW/3V3,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1076TW/3V3,112 is usually 5 days.
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Once your UJA1076TW/3V3,112 order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for UJA1076TW/3V3,112?
For technical support, including UJA1076TW/3V3,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1076TW/3V3,112 requirements.
6.How does Aetrix verify that UJA1076TW/3V3,112 is sourced from the original manufacturer or authorized distributors?
All UJA1076TW/3V3,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1076TW/3V3,112 meets industry standards.
7.What is the process for return or replacement of UJA1076TW/3V3,112?
All UJA1076TW/3V3,112 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1076TW/3V3,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1076TW/3V3,112 part is unused and in its original packaging.
Return procedure for UJA1076TW/3V3,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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