NXP Semiconductors UJA1078ATW/5V0/WD,
- Part No.:
- UJA1078ATW/5V0/WD,
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1078ATW/5V0/WD,.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1078ATW/5V0/WD from NXP Semiconductors is a high-speed CAN/dual LIN core System Basis Chip (SBC) integrating a 5 V/250 mA microcontroller regulator (V1), dedicated 5 V CAN transceiver regulator (V2), ISO 11898-2/5-compliant HS-CAN transceiver, two LIN 2.2A transceivers, SPI interface, advanced watchdog, and limp home output - deployed in automotive ECUs for powertrain and body control modules requiring robust bus wake-up and controlled startup.
For engineers reviewing the UJA1078ATW/5V0/WD datasheet, UJA1078ATW/5V0/WD pinout, UJA1078ATW/5V0/WD application, or UJA1078ATW/5V0/WD equivalent, key selection criteria include its dual-LIN + HS-CAN integration, 5 V V1 regulator with external PNP extension capability, ±58 V short-circuit proof bus pins, 16-bit SPI diagnostic interface, and watchdog with Window/Timeout modes - all in HTSSOP32 packaging compliant with ISO 7637-3 and IEC 61000-4-2 ESD standards.
Technical Context
The UJA1078ATW/5V0/WD implements a hierarchical power management architecture: V1 supplies the MCU at 5 V ±2 % with undervoltage warning at 90 % and reset at 90 % or 70 % of nominal; V2 independently powers the integrated CAN transceiver and remains stable down to 5.5 V during cranking. Its SPI interface operates full-duplex with register-mapped diagnostics including WD_and_Status, Mode_Control, and Int_Status registers.
Bus interface logic supports concurrent operation: HS-CAN transceiver features SPLIT pin for recessive-level stabilization and floating bus pins in Off mode; both LIN transceivers support low-slope mode (10.4 kbit/s) for EMC optimization and include integrated termination diodes (DLIN). Wake-up sources include CAN/LIN activity, two local inputs (WAKE1/WAKE2), and cyclic wake-up - all detectable and configurable via SPI.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V1 Output Voltage | 5 V ±2 % - powers MCU and peripherals; supports external PNP transistor for thermal load sharing above 250 mA threshold |
| V2 Output Voltage | 5 V - dedicated supply for on-chip HS-CAN transceiver; switchable off to reduce quiescent current |
| CAN Compliance | ISO 11898-2:2003 and ISO 11898-5:2006 - interoperable with TJA1042; bus pins withstand ±58 V short-circuit and ISO 7637-3 transients |
| LIN Compliance | LIN 2.2A and SAE J2602 - backward compatible to LIN 1.0; low-slope mode enables 10.4 kbit/s for improved EMC |
| Watchdog Modes | Window, Timeout (cyclic wake-up capable), and Off - clocked by on-chip oscillator; default period 128 ms |
| SPI Interface | 16-bit full-duplex - provides register access for configuration, status reporting (V1/V2 UV, wake-up source, interrupt flags), and system reset control |
| Package | HTSSOP32 (SOT549-1) - 6.1 mm × 11 mm, 0.65 mm pitch, exposed die pad for thermal dissipation; RoHS and dark green compliant |
Pinout & Package
UJA1078ATW/5V0/WD uses the HTSSOP32 (SOT549-1) package: thermally enhanced thin shrink small outline with 32 leads, 6.1 mm body width, 0.65 mm lead pitch, and exposed die pad soldered to PCB ground for optimal thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BAT (Pin 32) | Battery input supply | Primary power source for SBC; supports operation down to 4.5 V during cranking per ISO 7637/16750-2 |
| V1 (Pin 4) | Main MCU regulator output | 5 V ±2 % output delivering up to 250 mA; connects to external PNP transistor via VEXCTRL/VEXCC for extended current capability |
| V2 (Pin 20) | CAN transceiver regulator | Dedicated 5 V supply for internal HS-CAN transceiver; independent of V1 to improve EMC and fault isolation |
| RSTN (Pin 6) | Bidirectional reset | Active-low reset I/O with programmable power-on reset length; supports software-initiated system reset |
| INTN (Pin 7) | Interrupt output | Open-drain output signaling V1/V2 undervoltage, CAN/LIN/local wake-up, cyclic, and power-on events |
| WAKE1 / WAKE2 (Pins 18, 19) | Local wake-up inputs | Analog inputs with selectable 16 ms or 64 ms sampling; biasable via WBIAS (Pin 28) for low-current standby operation |
| LIMP (Pin 17) | Limp home control | Active-low output activating fail-safe hardware during critical faults; driven LOW automatically in Overtemp mode |
| SPLIT (Pin 24) | CAN common-mode stabilizer | Output connected to external 4.7 nF capacitor to stabilize recessive bus level and reduce ringing |
| DLIN (Pin 26) | LIN termination diode node | Internal diode connection point for LIN bus termination; simplifies external circuitry for LIN1/LIN2 networks |
| TXDC / RXDC (Pins 13, 14) | CAN data interface | Digital inputs/outputs connecting to MCU's CAN controller; enable full-duplex HS-CAN communication |
| TXDL1 / RXDL1 / TXDL2 / RXDL2 (Pins 3, 5, 1, 2) | LIN data interfaces | Four digital signals supporting two independent LIN channels; each pair connects to separate LIN controller peripherals |
| SDI / SDO / SCK / SCSN (Pins 9, 10, 11, 12) | SPI interface | Full-duplex serial interface for configuration, diagnostics, and real-time status monitoring with register-level access |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent LIN transceivers | Both comply with LIN 2.2A and SAE J2602; support low-slope mode (10.4 kbit/s) and integrated DLIN termination diode for simplified board layout |
| High-speed CAN transceiver with SPLIT pin | ISO 11898-2/5 compliant; SPLIT output stabilizes recessive bus voltage using external capacitor - reduces bus reflections and improves signal integrity |
| Scalable 5 V/250 mA V1 regulator | ±2 % accuracy with undervoltage warning at 90 % and configurable reset threshold (90 % or 70 %); external PNP extension enables >250 mA load with distributed thermal dissipation |
| Advanced watchdog with independent clock | On-chip oscillator-based timing; supports Window mode (prevents premature or late triggers) and Timeout mode with optional cyclic wake-up - enhances system reliability without MCU dependency |
| Comprehensive wake-up architecture | Supports bus wake-up (CAN/LIN), two local inputs (WAKE1/WAKE2), and cyclic wake-up; wake-source detection reported via SPI-interrupt flags and status registers |
| Limp home and overtemperature protection | LIMP output driven LOW during Overtemp mode or serious malfunction; automatic overtemperature shutdown at Tth(act)otp with hysteresis-based recovery |
Applications
| Powertrain Control Module | Body Control Module |
|---|---|
|
Use Scenario: Centralized ECU managing engine sensors, actuators, and transmission control via CAN backbone with LIN sub-networks for throttle, coolant, and exhaust subsystems. IC Role / Device Role / Timing Role: Core SBC providing regulated 5 V power to MCU, HS-CAN physical layer connectivity, dual LIN interfaces for sensor clusters, and safe startup/shutdown sequencing. Use Value: Eliminates discrete regulators, transceivers, and watchdog ICs - reducing BOM count, PCB area, and design validation effort while meeting ISO 26262 ASIL-B readiness requirements. |
Use Scenario: Vehicle body domain controller coordinating door locks, lighting, HVAC, and window motors using CAN for inter-module communication and LIN for low-cost peripheral control. IC Role / Device Role / Timing Role: Power management and bus interface hub supplying MCU, enabling remote flash programming over CAN, and detecting LIN bus wake-up for sleep-to-active transitions. Use Value: Enables ultra-low sleep current (<100 µA) with full wake-up capability via CAN/LIN/local inputs - extending battery life in always-on vehicle architectures. |
| Chassis Control Unit | ADAS Sensor Hub |
|
Use Scenario: Brake-by-wire or electronic stability control ECU requiring deterministic CAN messaging, redundant power supervision, and fail-safe limp-home activation under fault conditions. IC Role / Device Role / Timing Role: Safety-critical SBC delivering independent V1/V2 regulation, overtemperature shutdown, LIMP output assertion, and bidirectional RSTN with programmable timing. Use Value: Provides hardware-enforced safety mechanisms - including V1/V2 undervoltage detection, interrupt-driven fault reporting, and automatic LIMP activation - reducing software safety burden. |
Use Scenario: Fusion ECU aggregating radar, camera, and ultrasonic sensor data, where LIN networks manage individual sensor nodes and CAN links to central ADAS processor. IC Role / Device Role / Timing Role: Dual-LIN master interface with low-slope mode for noise-immune sensor communication, HS-CAN gateway functionality, and SPI-based diagnostics for sensor health monitoring. Use Value: LIN low-slope mode (10.4 kbit/s) minimizes radiated emissions near sensitive RF components; SPI register access enables real-time sensor status polling without disrupting CAN traffic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar core SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1076ATW/5V0/WD | Single-LIN variant (one LIN transceiver); identical V1/V2 regulators, CAN, SPI, watchdog, and HTSSOP32 package | Suitable for ECUs requiring only one LIN sub-bus; lower pin count and reduced LIN routing complexity | Select UJA1076ATW/5V0/WD when dual-LIN is unnecessary - reduces PCB routing density and simplifies firmware handling of LIN peripherals |
| TJA1128BK/0Z | Standalone HS-CAN transceiver (no LIN, no regulators, no watchdog); ISO 11898-2/5 compliant; SO14 package | Used only for CAN physical layer extension; requires external regulators, LIN transceivers, and supervision ICs | Choose TJA1128BK/0Z when modular architecture is preferred - allows independent scaling of power, CAN, and LIN resources across multiple ECUs |
Compared with UJA1078ATW/5V0/WD, UJA1076ATW/5V0/WD reduces system integration by removing one LIN channel but retains identical power and CAN capabilities, whereas TJA1128BK/0Z offers pure CAN PHY functionality without integrated regulation or multi-bus support - requiring additional components to match UJA1078ATW/5V0/WD's consolidated feature set.
Availability
UJA1078ATW/5V0/WD is available at Aetrix Electronics and suitable for automotive powertrain control, body electronics, chassis systems, and ADAS sensor hubs requiring stable component supply, long-term lifecycle support, and AEC-Q100 qualified silicon.
Supply support for UJA1078ATW/5V0/WD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications - with deep expertise in automotive-grade analog, mixed-signal, and system basis chips.
The UJA1078ATW/5V0/WD belongs to NXP's Core System Basis Chip product line, designed specifically to consolidate power management, high-speed CAN, dual LIN, and safety supervision functions into a single AEC-Q100 qualified device for next-generation automotive ECUs.
FAQ
What is the output voltage tolerance and current capability of the main regulator (V1) in UJA1078ATW/5V0/WD?
The UJA1078ATW/5V0/WD features a 5 V main regulator (V1) with ±2 % output voltage accuracy across temperature and load. It delivers up to 250 mA continuously and supports extension via an external PNP transistor - with programmable activation thresholds (50 mA or 85 mA rising, 15 mA or 50 mA falling) to distribute thermal load across the PCB. This ensures stable MCU supply even under cranking conditions down to 4.5 V.
Does UJA1078ATW/5V0/WD support remote firmware updates over the CAN bus?
Yes, UJA1078ATW/5V0/WD supports remote flash programming via the CAN bus. Its integrated HS-CAN transceiver complies with ISO 11898-2:2003 and ISO 11898-5:2006, enabling robust communication for bootloader execution and firmware updates - a key requirement for OTA-capable automotive ECUs. The SBC maintains safe startup behavior and power sequencing during update cycles.
How does the watchdog in UJA1078ATW/5V0/WD differ from basic timeout watchdogs?
The UJA1078ATW/5V0/WD watchdog uses an on-chip oscillator for independent timing and supports three modes: Window (detects early/late triggers), Timeout (with optional cyclic wake-up), and Off. Unlike basic timeout watchdogs, its Window mode prevents both premature and delayed resets - enhancing system reliability in safety-critical automotive applications where deterministic behavior is mandatory.
What LIN protocol versions are supported by UJA1078ATW/5V0/WD, and how is EMC optimized?
UJA1078ATW/5V0/WD supports LIN 2.2A and SAE J2602, with full backward compatibility to LIN 1.0 through LIN 2.2. EMC is optimized via low-slope mode (10.4 kbit/s), which reduces edge rates and radiated emissions - particularly beneficial in dense automotive harnesses. Each LIN transceiver also integrates a termination diode at DLIN to simplify external circuitry and improve signal integrity.
Can UJA1078ATW/5V0/WD operate during automotive battery cranking events?
Yes, UJA1078ATW/5V0/WD is designed for automotive cranking resilience: V1 regulator operates down to 4.5 V and V2 down to 5.5 V, both compliant with ISO 7637-2 and ISO 16750-2. Its ±58 V short-circuit proof CAN/LIN pins and transient protection per ISO 7637-3 ensure reliable operation during severe voltage dips and load dump events typical in 12 V vehicle electrical systems.
UJA1078ATW/5V0/WD, Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- -
- Interface:
- CAN, LIN
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1078ATW/5V0/WD, FAQ
1.How can I place an order for UJA1078ATW/5V0/WD, through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1078ATW/5V0/WD, on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1078ATW/5V0/WD, reliable?
The price and inventory of UJA1078ATW/5V0/WD, are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1078ATW/5V0/WD, is usually 5 days.
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Once your UJA1078ATW/5V0/WD, order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1078ATW/5V0/WD,?
For technical support, including UJA1078ATW/5V0/WD, datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1078ATW/5V0/WD, requirements.
6.How does Aetrix verify that UJA1078ATW/5V0/WD, is sourced from the original manufacturer or authorized distributors?
All UJA1078ATW/5V0/WD, products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1078ATW/5V0/WD, meets industry standards.
7.What is the process for return or replacement of UJA1078ATW/5V0/WD,?
All UJA1078ATW/5V0/WD, units undergo pre-shipment inspection (PSI). If there is an issue with UJA1078ATW/5V0/WD,, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1078ATW/5V0/WD, part is unused and in its original packaging.
Return procedure for UJA1078ATW/5V0/WD,:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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