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Home > Products > Integrated Circuits (ICs) > Interface > Specialized

NXP Semiconductors UJA1079ATW/3V3/1J

Name: UJA1079ATW/3V3/1J
Brand: NXP Semiconductors
SKU: UJA1079ATW/3V3/1J
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: UJA1079ATW/3V3/1J

Manufacturer:: NXP Semiconductors

Category:: Specialized

Package:: 32-TSSOP (0.240", 6.10mm Width) Exposed Pad

Datasheet:: UJA1079ATW/3V3/1J.pdf

Description:: IC INTFACE SPECIALIZED 32HTSSOP

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Product details

Overview

UJA1079ATW/3V3/1J from NXP Semiconductors is a LIN core System Basis Chip (SBC) integrating a LIN 2.2A transceiver, 3.3 V ±2 % voltage regulator (250 mA), advanced watchdog with Window/Timeout/Off modes, SPI interface, and dual local wake-up inputs. It serves as the power management and communication hub for automotive ECUs in body control modules, door modules, and seat control units.

For engineers reviewing the UJA1079ATW/3V3/1J datasheet, UJA1079ATW/3V3/1J pinout, UJA1079ATW/3V3/1J application, or UJA1079ATW/3V3/1J equivalent, this page delivers verified functional architecture, thermal-aware regulator behavior, LIN bus fault protection (±58 V short-circuit proof), and precise wake-up source detection logic - all critical for ECU reliability validation and ISO 26262-compliant system design.

Technical Context

The UJA1079ATW/3V3/1J implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp mode transitions triggered by VBAT thresholds, LIN activity, or local wake-up events. Its LIN transceiver supports low-slope mode (10.4 kbit/s) for optimized EMC and includes integrated termination diode at DLIN.

Power management features include V1 undervoltage warning at 90 % of nominal output, selectable reset threshold (90 % or 70 %), and external PNP transistor control via VEXCTRL/VEXCC pins with programmable activation current thresholds (50 mA/85 mA). The on-chip oscillator independently clocks the watchdog, decoupling timing integrity from V1 stability.

Key Specifications

Parameter	Value and Actual Design Meaning
LIN Compliance	LIN 2.2A, SAE J2602, backward compatible to LIN 1.0; enables interoperability across legacy and new automotive sub-networks.
V1 Regulator Output	3.3 V ±2 %, 250 mA max; powers microcontroller and peripherals; stable down to VBAT = 4.5 V during cranking per ISO 16750-2.
Watchdog Modes	Window, Timeout, Off; configurable via WMC bit and WDOFF pin; default period 128 ms; independent on-chip oscillator clock source.
SPI Interface	16-bit full-duplex; register read/write access; supports status feedback during configuration; SCSN active-low, SCK idle-low.
Wake-up Inputs	WAKE1/WAKE2 analog inputs with programmable sampling (16 ms/64 ms); wake-source detection reported via WD_and_Status register bits WLS1/WLS2.
Protection Ratings	±58 V short-circuit proof LIN pin; ±8 kV HBM ESD on LIN/WAKE pins; ISO 7637-3 transient protection; overtemperature shutdown with hysteresis.
Package	HTSSOP32 (SOT549-1); 6.1 mm × 11 mm; exposed die pad for enhanced thermal dissipation; RoHS and dark green compliant.

Pinout & Package

HTSSOP32 package (SOT549-1) with 0.65 mm lead pitch and thermally enhanced exposed die pad soldered to PCB ground for optimal thermal and electrical performance.

Pin/Terminal	Circuit Role	Design Meaning
BAT (Pin 32)	Battery supply input	Primary power source for SBC; supports operation down to 4.5 V during engine cranking per ISO 16750-2.
V1 (Pin 4)	Regulated output	3.3 V ±2 % supply for microcontroller and peripherals; undervoltage warning/reset thresholds configurable via RSTN pull-up.
LIN (Pin 25)	LIN bus interface	Half-duplex bidirectional LIN physical layer connection; ±58 V short-circuit protected; ISO 7637-3 transient hardened.
RXDL (Pin 5)	LIN receive data output	Logic-level signal indicating LIN bus activity; used for wake-up detection and protocol decoding by MCU.
TXDL (Pin 3)	LIN transmit data input	Drives LIN bus via internal driver; slope controlled via LSC bit (normal: 20 kbit/s, low: 10.4 kbit/s).
WAKE1/WAKE2 (Pins 18,19)	Local wake-up inputs	Analog inputs detecting switch closures; sampling time selectable (16 ms/64 ms); wake-source identification via status register.
RSTN (Pin 6)	Bidirectional reset	Microcontroller-initiated reset (LOW pulse) or SBC-generated reset pulse; length configurable via external pull-up resistor.
INTN (Pin 7)	Interrupt output	Open-drain signal indicating V1 undervoltage, LIN/local wake-up, cyclic, or power-on events; individually maskable.
EN (Pin 8)	Global enable output	Fail-safe control signal to enable/disable safety-critical hardware; driven HIGH only in Normal mode when ENC = 1.
LIMP (Pin 17)	Limp home output	Active-Low fail-safe output activated during Overtemp mode or software-triggered limp home; drives external hardware directly.
WDOFF (Pin 16)	Watchdog disable input	Hardware override: HIGH disables watchdog regardless of WMC setting; change triggers immediate system reset in Normal/Standby.
SDI/SDO/SCK/SCSN (Pins 9,10,11,12)	SPI interface	Full-duplex serial link for register configuration, status reading, and diagnostics; supports read-only access to preserve state.
VEXCTRL/VEXCC (Pins 31,29)	External PNP control	VEXCTRL drives base of external PNP; VEXCC measures collector current; enables scalable current delivery beyond 250 mA with distributed thermal load.
DLIN (Pin 26)	LIN termination diode	Integrated diode connects to external 1 kΩ termination resistor; eliminates need for discrete diode in LIN bus node design.
WBIAS (Pin 28)	Wake bias control	Provides bias current for external wake-up switches; sampling time synchronized to WBIAS when WSEn = 1 (16 ms or 64 ms).

Key Features

Feature	Design Value
Advanced low-power concept	Standby current < 100 µA and Sleep current < 20 µA with full wake-up capability via LIN or local inputs - extends battery life in always-on ECU nodes.
Safe and controlled system start-up	Power-on reset pulse width configurable via RSTN pull-up; ensures deterministic microcontroller initialization before V1 stabilizes.
Detailed status reporting	Register-mapped diagnostics (WD_and_Status, Int_Status) provide real-time visibility into V1 health, wake-source origin, and interrupt sources.
LIN bus EMC optimization	Low-slope mode (10.4 kbit/s) reduces radiated emissions; integrated termination diode simplifies layout and improves signal integrity.
Thermal-aware regulator extension	External PNP transistor support with programmable current thresholds (50/85 mA) enables >250 mA load handling while distributing heat across PCB.

Applications

Body Control Module (BCM)	Door Control Unit (DCU)
Use Scenario: Centralized control of lighting, window lifts, locks, and mirrors in passenger vehicles. IC Role / Device Role / Timing Role: UJA1079ATW/3V3/1J acts as primary power manager and LIN interface, supplying 3.3 V to MCU and relaying commands between LIN master and local actuators. Use Value: Integrated watchdog and undervoltage monitoring ensure fail-safe operation during battery transients; ±58 V LIN protection prevents damage from load dump events.	Use Scenario: Local ECU managing power windows, central locking, and mirror adjustment via LIN sub-bus. IC Role / Device Role / Timing Role: UJA1079ATW/3V3/1J provides regulated 3.3 V power, LIN transceives commands, and detects mechanical switch closures via WAKE1/WAKE2 inputs. Use Value: Programmable wake-up sampling (16/64 ms) minimizes current draw while reliably detecting slow-switch bounce; LIMP output activates safe fallback behavior on thermal fault.
Seat Control Module	Roof Module (Sunroof/Blind)
Use Scenario: Motorized seat position memory and adjustment using LIN-connected sensors and actuators. IC Role / Device Role / Timing Role: UJA1079ATW/3V3/1J supplies MCU and motor drivers, monitors LIN bus for position commands, and reports faults via SPI-integrated diagnostics. Use Value: SPI full-duplex interface enables real-time register access for position calibration and error logging; overtemperature shutdown prevents thermal runaway in enclosed seat cavities.	Use Scenario: Sunroof or power blind actuation controlled via LIN network with anti-pinch safety logic. IC Role / Device Role / Timing Role: UJA1079ATW/3V3/1J manages power sequencing, LIN communication with body domain, and local wake-up from rain sensor or manual switch. Use Value: Dual wake-up inputs (WAKE1/WAKE2) support redundant sensing; EN output disables motor drivers during fault conditions per ASIL-B requirements.

Body Control Module (BCM)

Door Control Unit (DCU)

Use Scenario: Centralized control of lighting, window lifts, locks, and mirrors in passenger vehicles.

IC Role / Device Role / Timing Role: UJA1079ATW/3V3/1J acts as primary power manager and LIN interface, supplying 3.3 V to MCU and relaying commands between LIN master and local actuators.

Use Value: Integrated watchdog and undervoltage monitoring ensure fail-safe operation during battery transients; ±58 V LIN protection prevents damage from load dump events.

Use Scenario: Local ECU managing power windows, central locking, and mirror adjustment via LIN sub-bus.

IC Role / Device Role / Timing Role: UJA1079ATW/3V3/1J provides regulated 3.3 V power, LIN transceives commands, and detects mechanical switch closures via WAKE1/WAKE2 inputs.

Use Value: Programmable wake-up sampling (16/64 ms) minimizes current draw while reliably detecting slow-switch bounce; LIMP output activates safe fallback behavior on thermal fault.

Seat Control Module

Roof Module (Sunroof/Blind)

Use Scenario: Motorized seat position memory and adjustment using LIN-connected sensors and actuators.

IC Role / Device Role / Timing Role: UJA1079ATW/3V3/1J supplies MCU and motor drivers, monitors LIN bus for position commands, and reports faults via SPI-integrated diagnostics.

Use Value: SPI full-duplex interface enables real-time register access for position calibration and error logging; overtemperature shutdown prevents thermal runaway in enclosed seat cavities.

Use Scenario: Sunroof or power blind actuation controlled via LIN network with anti-pinch safety logic.

IC Role / Device Role / Timing Role: UJA1079ATW/3V3/1J manages power sequencing, LIN communication with body domain, and local wake-up from rain sensor or manual switch.

Use Value: Dual wake-up inputs (WAKE1/WAKE2) support redundant sensing; EN output disables motor drivers during fault conditions per ASIL-B requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LIN SBC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
UJA1076ATW/3V3/1J	Single wake-up input (WAKE1 only); no LIMP output; identical LIN transceiver and 3.3 V regulator specs.	Suitable for cost-sensitive nodes without limp-home requirement or dual-sensor wake-up needs.	Select when system-level fail-safe output and second wake channel are unnecessary; reduces BOM count and layout area.
TLE9263BQX	5 V regulator only; integrates CAN FD transceiver alongside LIN; higher quiescent current in Standby (>150 µA).	Targeted at mixed LIN/CAN domains (e.g., gateway modules); not drop-in for pure LIN nodes requiring 3.3 V supply.	Choose when co-location of LIN and CAN FD is required; avoid if 3.3 V regulation or ultra-low standby current (<100 µA) is mandatory.

Compared with UJA1079ATW/3V3/1J, UJA1076ATW/3V3/1J reduces feature set for cost savings but sacrifices limp-home safety and dual wake-up flexibility, while TLE9263BQX adds CAN FD at the expense of 3.3 V support and higher static current - making UJA1079ATW/3V3/1J optimal for dedicated, safety-conscious LIN nodes demanding 3.3 V regulation and thermal resilience.

Availability

UJA1079ATW/3V3/1J is available at Aetrix Electronics and suitable for automotive body electronics, door control systems, and seat modules requiring stable component supply, long-term lifecycle assurance, and AEC-Q100 Grade 1 qualification.

Supply support for UJA1079ATW/3V3/1J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade power management and networking ICs.

The UJA1079ATW/3V3/1J belongs to NXP's LIN System Basis Chip product line, engineered specifically for robust, low-power ECU designs in automotive body electronics where integration, fault resilience, and ISO 26262 alignment are critical.

FAQ

What LIN protocol versions does the UJA1079ATW/3V3/1J support?

The UJA1079ATW/3V3/1J supports LIN 2.2A and SAE J2602, and is fully backward compatible with LIN 2.2, LIN 2.1, LIN 2.0, and LIN 1.3 through LIN 1.0. This broad compatibility ensures seamless integration into both legacy and next-generation automotive LIN networks without firmware updates to the master node.

How does the UJA1079ATW/3V3/1J handle undervoltage conditions on its V1 output?

The UJA1079ATW/3V3/1J provides two-tiered V1 monitoring: an undervoltage warning flag (V1S bit) asserts when output drops below 90 % of nominal (2.97 V), and a reset is triggered at either 90 % or 70 % (2.31 V) depending on RTHC bit setting. The reset pulse width is externally configurable via the RSTN pull-up resistor, enabling precise MCU reset timing alignment.

Can the UJA1079ATW/3V3/1J drive more than 250 mA to the microcontroller?

Yes - the UJA1079ATW/3V3/1J supports external current boosting via an external PNP transistor connected to VEXCTRL and VEXCC pins. With programmable activation thresholds (50 mA or 85 mA rising/falling), it seamlessly extends output capability beyond 250 mA while distributing thermal load across the PCB, maintaining safe junction temperatures under sustained load.

What is the purpose of the DLIN pin on the UJA1079ATW/3V3/1J?

The DLIN pin on the UJA1079ATW/3V3/1J connects to an external 1 kΩ termination resistor and integrates a built-in diode that replaces the discrete diode traditionally required in LIN bus node designs. This reduces component count, simplifies PCB layout, and improves reliability by eliminating a potential failure point in the LIN termination network.

Does the UJA1079ATW/3V3/1J support wake-up from Sleep mode using only the LIN bus?

Yes - the UJA1079ATW/3V3/1J supports LIN bus wake-up from Sleep mode when STBCL = 1 (Lowpower mode enabled). In this configuration, the LIN transceiver remains in a low-power listening state with wake-up detection active, allowing the SBC to transition to Standby mode and assert a system reset upon valid LIN header detection - all while consuming <20 µA.

How is watchdog behavior configured in Standby mode on the UJA1079ATW/3V3/1J?

In Standby mode, the UJA1079ATW/3V3/1J watchdog operates in Timeout mode if WMC = 0, or Off mode if WMC = 1. The WDOFF pin overrides software control: pulling it HIGH disables the watchdog regardless of WMC, and any change in WDOFF state triggers an immediate system reset - ensuring deterministic fault response even during low-power states.

UJA1079ATW/3V3/1J Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: -

Package/Case:: 32-TSSOP (0.240", 6.10mm Width) Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Not For New Designs

Applications:: -

Interface:: SPI Serial

Voltage - Supply:: 4.5V ~ 28V

Supplier Device Package:: 32-HTSSOP

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

UJA1079ATW/3V3/1J FAQ

1.How can I place an order for UJA1079ATW/3V3/1J through Aetrix?

Please submit a Request for Quotation (RFQ) for UJA1079ATW/3V3/1J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for UJA1079ATW/3V3/1J reliable?

The price and inventory of UJA1079ATW/3V3/1J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1079ATW/3V3/1J is usually 5 days.

3.What payment methods are accepted for UJA1079ATW/3V3/1J?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1079ATW/3V3/1J transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for UJA1079ATW/3V3/1J?

UJA1079ATW/3V3/1J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your UJA1079ATW/3V3/1J order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for UJA1079ATW/3V3/1J?

For technical support, including UJA1079ATW/3V3/1J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1079ATW/3V3/1J requirements.

6.How does Aetrix verify that UJA1079ATW/3V3/1J is sourced from the original manufacturer or authorized distributors?

All UJA1079ATW/3V3/1J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1079ATW/3V3/1J meets industry standards.

7.What is the process for return or replacement of UJA1079ATW/3V3/1J?

All UJA1079ATW/3V3/1J units undergo pre-shipment inspection (PSI). If there is an issue with UJA1079ATW/3V3/1J, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The UJA1079ATW/3V3/1J part is unused and in its original packaging.

Return procedure for UJA1079ATW/3V3/1J:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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