NXP Semiconductors UJA1079ATW/3V3/WD,
- Part No.:
- UJA1079ATW/3V3/WD,
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1079ATW/3V3/WD,.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,180
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UJA1079ATW/3V3/WD from NXP Semiconductors is a LIN core System Basis Chip (SBC) integrating a LIN 2.2A/SAE J2602 transceiver, 3.3 V ±2 % voltage regulator delivering up to 250 mA, advanced window/timeout watchdog with on-chip oscillator, SPI interface, dual local wake-up inputs, and limp home output - designed for automotive ECU power management and communication control in body electronics modules.
For engineers reviewing the UJA1079ATW/3V3/WD datasheet, UJA1079ATW/3V3/WD pinout, UJA1079ATW/3V3/WD application, or UJA1079ATW/3V3/WD equivalent, this SBC delivers verified LIN bus compliance, configurable wake-up sampling (16 ms/64 ms), ±58 V short-circuit protected LIN pin, ISO 7637-3 transient protection, and thermal shutdown - critical for robust automotive sub-bus node design.
Technical Context
The UJA1079ATW/3V3/WD implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp mode transitions triggered by VBAT thresholds, wake events, or register-controlled MC bits. Its LIN transceiver supports low-slope (10.4 kbit/s) and normal-slope (20 kbit/s) modes with integrated DLIN termination diode and ±8 kV HBM ESD protection.
Power management includes V1 regulation down to 4.5 V battery input (ISO 16750-2 cranking), programmable external PNP transistor activation (Ith(act) = 50 mA or 85 mA), and undervoltage detection at 90 % or 70 % of nominal output. The watchdog operates independently via on-chip oscillator and supports cyclic interrupt generation in Timeout mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LIN Compliance | LIN 2.2A and SAE J2602 compliant; backward compatible to LIN 1.0–2.2 - ensures interoperability across legacy and modern automotive LIN networks. |
| Voltage Regulator Output | 3.3 V ±2 %, 250 mA max - powers microcontroller and peripherals; supports external PNP transistor for thermal load sharing. |
| Watchdog Modes | Window, Timeout, and Off modes; default period 128 ms - enables fail-safe timing supervision with configurable reset behavior. |
| SPI Interface | 16-bit full-duplex SPI with read-only register access - allows real-time configuration, status reporting, and diagnostics without unintended register modification. |
| Wake-up Inputs | WAKE1 and WAKE2 with selectable 16 ms or 64 ms sampling - reduces current draw during Standby while maintaining reliable switch detection. |
| Thermal & Electrical Protection | ±58 V short-circuit proof LIN pin; ISO 7637-3 transient immunity; overtemperature shutdown - meets automotive environmental stress requirements. |
| Package | HTSSOP32 (6.1 mm × 11 mm); exposed die pad - provides low thermal resistance for high-reliability underhood operation. |
Pinout & Package
Package: HTSSOP32 (SOT549-1), plastic thermal enhanced thin shrink small outline package with 32 leads, 0.65 mm pitch, 6.1 mm body width, and exposed die pad soldered to PCB ground for optimal thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BAT (Pin 32) | Battery supply input | Accepts 4.5 V–27 V automotive battery range; powers internal circuitry and enables operation during cranking per ISO 16750-2. |
| V1 (Pin 4) | Regulated output | 3.3 V ±2 %, up to 250 mA; supplies microcontroller and peripherals; undervoltage warning/reset configurable at 90 % or 70 % threshold. |
| LIN (Pin 25) | LIN bus interface | AIO pin supporting active bus communication and wake-up detection; ±58 V short-circuit protected and ISO 7637-3 transient hardened. |
| RSTN (Pin 6) | Bidirectional reset | Drives LOW for system reset; supports variable power-on reset length via external pull-up; handles both internal and external reset events. |
| WAKE1 / WAKE2 (Pins 18, 19) | Local wake-up inputs | Analog inputs with programmable sampling; enable wake-up from Standby/Sleep via external switches without LIN bus activity. |
| LIMP (Pin 17) | Limp home output | Active-low fail-safe output activated during Overtemp or serious malfunction - triggers hardware-level fallback functionality. |
| WDOFF (Pin 16) | Watchdog disable control | Digital input; HIGH disables watchdog entirely - used for debug or safety-critical disable scenarios. |
| SDI/SDO/SCK/SCSN (Pins 9, 10, 11, 12) | SPI interface | Full-duplex serial interface for register access; supports read-only mode to prevent accidental configuration changes. |
Key Features
| Feature | Design Value |
|---|---|
| LIN Transceiver Integration | Single-chip LIN 2.2A/SAE J2602 solution eliminates discrete transceiver + termination + protection components - reduces BOM count and PCB area in ECU designs. |
| Scalable Power Delivery | V1 regulator supports external PNP transistor with user-selectable activation thresholds (50 mA/85 mA) - distributes heat across PCB and extends thermal margin for sustained 250 mA loads. |
| Intelligent Wake-up Management | WBIAS-controlled biasing and dual wake-up inputs with configurable sampling intervals - minimizes quiescent current in Standby while ensuring reliable switch detection. |
| Fail-Safe System Control | Dedicated EN (global enable) and LIMP (limp home) outputs - provide hardware-level control paths independent of microcontroller firmware for functional safety compliance. |
| Robust Automotive Qualification | ±8 kV HBM ESD, ±6 kV IEC 61000-4-2, ISO 7637-3 transient immunity, and -40 °C to +150 °C junction temperature rating - validated for underhood deployment. |
Applications
| Door Module Control | Seat Position Memory |
|---|---|
Use Scenario: Centralized door ECU managing window lift, lock actuation, mirror adjustment, and interior lighting via LIN sub-network. IC Role / Device Role / Timing Role: UJA1079ATW/3V3/WD serves as primary power manager and LIN interface - regulating MCU supply, enabling bus wake-up, and asserting LIMP during fault conditions. Use Value: Eliminates discrete LDO, transceiver, and watchdog; supports cranking down to 4.5 V; reduces standby current via synchronized wake-up sampling. | Use Scenario: Seat control module storing and recalling driver position settings using LIN-connected sensors and actuators. IC Role / Device Role / Timing Role: UJA1079ATW/3V3/WD provides regulated 3.3 V power to MCU and LIN transceiver, monitors seat switch inputs via WAKE1/WAKE2, and signals faults via LIMP. Use Value: Enables reliable local wake-up from Sleep mode without bus traffic; ±58 V LIN pin withstands load dump; SPI allows runtime diagnostics of position sensor data path. |
| Roof Console Lighting | Climate Control Actuator |
Use Scenario: Roof-mounted console with ambient lighting, sunroof control, and map lights coordinated over LIN. IC Role / Device Role / Timing Role: UJA1079ATW/3V3/WD acts as LIN node power hub - supplying MCU, handling LIN frame transmission/reception, and managing wake-up from key fob or touch sensor inputs. Use Value: Low-slope LIN mode (10.4 kbit/s) improves EMC in densely wired cabin environments; WBIAS pin simplifies external wake-up transistor biasing. | Use Scenario: HVAC actuator controlling blend door, mode door, and recirculation flaps via LIN commands from main climate ECU. IC Role / Device Role / Timing Role: UJA1079ATW/3V3/WD delivers stable 3.3 V power, interfaces LIN commands, detects motor stall via V1 undervoltage monitoring, and asserts LIMP on thermal overload. Use Value: Overtemperature shutdown protects against actuator jamming; undervoltage reset at 70 % threshold prevents erratic motor behavior during brownout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LIN SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1076ATW/3V3/WD | No LIMP output; single wake-up input (WAKE1 only); no VEXCTRL/VEXCC pins for external PNP control. | Suitable for cost-sensitive LIN nodes without limp-home requirement or high-current MCU loads. | Select UJA1076ATW/3V3/WD when limp home functionality and external PNP support are unnecessary - reduces system complexity and cost. |
| TLE9183QVXUMA1 | 5 V regulator only; integrated CAN transceiver; higher quiescent current in Standby (25 µA vs. UJA1079ATW/3V3/WD's 15 µA). | Targeted at mixed LIN/CAN gateways or nodes requiring dual-bus capability; not drop-in for 3.3 V–only designs. | Choose TLE9183QVXUMA1 only if CAN integration and 5 V supply are required - incompatible with 3.3 V MCU systems without level-shifting. |
Compared with UJA1079ATW/3V3/WD, UJA1076ATW/3V3/WD omits limp home and external PNP control for simpler nodes, while TLE9183QVXUMA1 adds CAN but lacks 3.3 V regulation - making UJA1079ATW/3V3/WD the optimal choice for dedicated 3.3 V LIN ECU designs requiring fail-safe fallback and thermal scalability.
Availability
UJA1079ATW/3V3/WD is available at Aetrix Electronics and suitable for automotive body electronics, seat control modules, and roof console systems requiring stable component supply, AEC-Q100 qualification, and long-term production continuity.
Supply support for UJA1079ATW/3V3/WD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications - with deep expertise in automotive-grade analog and mixed-signal ICs.
The UJA1079ATW/3V3/WD belongs to NXP's System Basis Chip product line, engineered specifically for LIN-based automotive ECUs to consolidate power, communication, and safety functions into a single AEC-Q100 qualified device.
FAQ
What LIN protocol versions does the UJA1079ATW/3V3/WD support?
The UJA1079ATW/3V3/WD supports LIN 2.2A and SAE J2602, and is backward compatible with LIN 2.2, LIN 2.1, LIN 2.0, LIN 1.3, LIN 1.2, LIN 1.1, and LIN 1.0. This broad compatibility ensures seamless integration into legacy and next-generation automotive LIN networks without protocol translation layers.
Does the UJA1079ATW/3V3/WD include a built-in watchdog, and how is it configured?
Yes, the UJA1079ATW/3V3/WD includes an advanced independent watchdog with Window, Timeout, and Off modes, clocked by an on-chip oscillator. It is configured via the WD_and_Status register (bits WMC and NWP) and controlled by the WDOFF pin. The default watchdog period is 128 ms, and mode selection is fully programmable through SPI.
Can the UJA1079ATW/3V3/WD operate during automotive battery cranking conditions?
Yes, the UJA1079ATW/3V3/WD operates down to 4.5 V on the BAT pin, meeting ISO 16750-2 cranking requirements. Its V1 regulator maintains stable 3.3 V output under these conditions, and the LIN transceiver remains functional - ensuring uninterrupted communication and wake-up capability during engine start.
How does the UJA1079ATW/3V3/WD handle thermal overload protection?
When the junction temperature exceeds the overtemperature protection activation threshold (Tth(act)otp), the UJA1079ATW/3V3/WD enters Overtemp mode: V1 is disabled, LIN is set to high-impedance, RSTN is driven LOW, and the LIMP pin is activated. Recovery requires temperature to fall below the hysteresis release threshold before returning to Standby with a system reset.
What is the purpose of the LIMP pin on the UJA1079ATW/3V3/WD, and when is it asserted?
The LIMP pin on the UJA1079ATW/3V3/WD is an active-low fail-safe output that activates during Overtemp mode or when the limp home warning bit (LHWC) is set and a subsequent reset occurs. It directly drives external 'limp home' hardware - such as backup lighting or simplified actuator control - to maintain basic functionality during critical system faults.
UJA1079ATW/3V3/WD, Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Applications:
- -
- Interface:
- SPI Serial
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1079ATW/3V3/WD, FAQ
1.How can I place an order for UJA1079ATW/3V3/WD, through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1079ATW/3V3/WD, on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1079ATW/3V3/WD, reliable?
The price and inventory of UJA1079ATW/3V3/WD, are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1079ATW/3V3/WD, is usually 5 days.
3.What payment methods are accepted for UJA1079ATW/3V3/WD,?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1079ATW/3V3/WD, transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1079ATW/3V3/WD,?
UJA1079ATW/3V3/WD, orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1079ATW/3V3/WD, order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1079ATW/3V3/WD,?
For technical support, including UJA1079ATW/3V3/WD, datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1079ATW/3V3/WD, requirements.
6.How does Aetrix verify that UJA1079ATW/3V3/WD, is sourced from the original manufacturer or authorized distributors?
All UJA1079ATW/3V3/WD, products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1079ATW/3V3/WD, meets industry standards.
7.What is the process for return or replacement of UJA1079ATW/3V3/WD,?
All UJA1079ATW/3V3/WD, units undergo pre-shipment inspection (PSI). If there is an issue with UJA1079ATW/3V3/WD,, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1079ATW/3V3/WD, part is unused and in its original packaging.
Return procedure for UJA1079ATW/3V3/WD,:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UJA1079ATW/3V3/WD, Tags

-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments

-
MD0100N8-G
Microchip Technology

-
PCA9548APW,118
NXP Semiconductors

-
PCA9540BDP,118
NXP Semiconductors

-
PCA9548APWR
Texas Instruments

-
PCA9546APW,118
NXP Semiconductors

-
PTN3360DBS,518
NXP Semiconductors

-
PCA9546ABS,118
NXP Semiconductors

-
PCA9518PWR
Texas Instruments

-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

