NXP Semiconductors UJA1079TW/5V0,118
- Part No.:
- UJA1079TW/5V0,118
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1079TW/5V0,118.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1079TW/5V0,118 from NXP Semiconductors is a LIN 2.1–compliant System Basis Chip (SBC) integrating a 5 V/250 mA voltage regulator, LIN transceiver, SPI interface, dual local wake-up inputs, and limp home output for automotive Electronic Control Units. It replaces discrete power, communication, and supervision components in LIN-based ECU designs, enabling controlled microcontroller startup and safe low-power operation.
For engineers reviewing the UJA1079TW/5V0,118 datasheet, UJA1079TW/5V0,118 pinout, UJA1079TW/5V0,118 application, or UJA1079TW/5V0,118 equivalent, this page delivers verified technical context, validated pin functions, automotive-grade EMC/ESD specs, thermal-aware regulator behavior, and precise watchdog timing modes - all confirmed for the /5V0 variant with HTSSOP32 package.
Technical Context
The UJA1079TW/5V0,118 implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp modes with deterministic transitions triggered by VBAT thresholds, LIN activity, wake pins, or temperature events. Its LIN transceiver supports active, low-power, and off states with programmable slope control (20 kbit/s normal / 10.4 kbit/s low-slope) and integrated DLIN termination diode.
Power management includes V1 undervoltage detection at 90 % or 70 % of nominal output, selectable external PNP activation thresholds (50/85 mA rising, 15/50 mA falling), and WBIAS-controlled 16 ms or 64 ms wake sampling. The on-chip oscillator independently clocks the watchdog, decoupling timing from V1 stability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LIN Compliance | LIN 2.1, SAE J2602, backward compatible with LIN 2.0 and LIN 1.3 - ensures interoperability with legacy and current automotive LIN networks. |
| Voltage Regulator Output | 5 V ±2 % (LIN master), ±3 % (LIN slave); 250 mA max - powers MCU and peripherals with accuracy meeting LIN master timing requirements. |
| Watchdog Modes | Window, Timeout, and Off modes; default 128 ms period; independent on-chip oscillator clock - enables fail-safe software supervision without external timing components. |
| SPI Interface | 16-bit full-duplex; SCSN/SDI/SCK/SDO signals; register-mapped access to WD_and_Status, Mode_Control, Int_Control - provides bidirectional configuration, status reporting, and interrupt handling with no protocol overhead. |
| Wake-up Capability | Two dedicated WAKE1/WAKE2 inputs with configurable edge detection and WBIAS bias control; supports 16 ms or 64 ms sampling - reduces standby current while maintaining reliable switch detection in battery-sensitive applications. |
| Thermal & Protection | ±58 V short-circuit proof LIN pin; ±8 kV HBM ESD; ISO 7637-3 transient protection; overtemperature shutdown with hysteresis - meets automotive environmental stress requirements without external protection circuitry. |
| Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm; 0.65 mm pitch; exposed die pad - enables high-power dissipation in compact ECU layouts with PCB-level thermal conduction. |
Pinout & Package
UJA1079TW/5V0,118 uses the HTSSOP32 (SOT549-1) thermally enhanced package with 32 leads, 6.1 mm body width, 0.65 mm lead pitch, and an exposed die pad for PCB heat sinking. The pad is electrically isolated and may be left floating or connected to GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 (Pin 4) | Regulated output supply | 5 V ±2 % output delivering up to 250 mA to MCU; supports external PNP extension for higher current and distributed thermal load. |
| RXDL (Pin 5) | LIN receive data output | Logic-level signal indicating LIN bus activity; used for wake-up detection and status monitoring in Lowpower mode. |
| RSTN (Pin 6) | Bidirectional reset I/O | Drives LOW during internal resets (V1 UV, watchdog, overtemp); accepts external LOW pulse for forced system reset; reset width configurable via pull-up. |
| INTN (Pin 7) | Interrupt output | Open-drain output signaling pending events: V1 undervoltage, LIN/local wake-up, cyclic interrupt, or power-on - enables prioritized MCU response. |
| EN (Pin 8) | Global enable output | Fail-safe control signal driven HIGH in Normal mode (configurable); used to enable safety-critical downstream circuitry only when SBC is fully operational. |
| WAKE1 (Pin 18), WAKE2 (Pin 19) | Local wake-up inputs | Dedicated digital inputs supporting edge-triggered interrupts; biasable via WBIAS (Pin 28) with selectable 16 ms or 64 ms sampling window. |
| LIMP (Pin 17) | Limp home output | Active-LOW open-drain output activated during Overtemp or software-configured failure - triggers hardware fallback mode without MCU intervention. |
| WDOFF (Pin 16) | Watchdog disable control | Hardware pin disabling watchdog when pulled HIGH; overrides software WMC setting - provides failsafe watchdog deactivation path. |
| DLIN (Pin 26) | LIN termination diode connection | Internal diode anode connection; external resistor to ground completes LIN bus termination - eliminates need for discrete termination component. |
| BAT (Pin 32) | Battery input supply | Accepts 4.5 V–27 V input; supports cranking (ISO 7637-4b) and reverse-battery protection; powers internal regulators and LIN transceiver directly. |
Key Features
| Feature | Design Value |
|---|---|
| LIN Transceiver with Low-Slope Mode | Reduces electromagnetic emissions by limiting slew rate to 10.4 kbit/s - improves EMC performance in noisy automotive environments without sacrificing protocol compliance. |
| Scalable 5 V Regulator with External PNP Support | Enables >250 mA total current delivery while distributing heat across PCB - avoids localized hotspots and extends reliability in sealed ECUs. |
| Programmable Watchdog with Independent Oscillator | Guarantees supervision even during V1 brownouts or MCU clock failures - eliminates single-point timing dependency in safety-critical systems. |
| Configurable Wake-up Sampling via WBIAS | Reduces average wake pin current by up to 75 % vs. continuous sampling - extends battery life in always-on vehicle modules (e.g., door controllers). |
| Integrated Limp Home Output with Overtemp Activation | Automatically asserts LIMP during thermal shutdown - enables immediate mechanical or functional fallback (e.g., headlight dimming, pump coast-down) without firmware involvement. |
| Full SPI Register Access with Read-Only Option | Allows non-destructive status readback (e.g., WD_and_Status, Int_Status) - simplifies diagnostic logging and avoids unintended register modification during debug. |
Applications
| Body Control Module (BCM) | Seat Position Controller |
|---|---|
Use Scenario: Centralized control of door locks, windows, mirrors, and interior lighting using LIN slaves. IC Role / Device Role / Timing Role: UJA1079TW/5V0,118 acts as the LIN master SBC, supplying regulated 5 V to MCU and transceivers while managing sleep/wake cycles and fault responses. Use Value: Enables ultra-low standby current (<100 µA) with reliable wake-on-LIN or local switch, reducing parasitic drain in parked vehicles. | Use Scenario: Motorized seat adjustment with position feedback, memory recall, and collision detection. IC Role / Device Role / Timing Role: UJA1079TW/5V0,118 provides fail-safe power sequencing, LIN communication, and limp-home activation if motor driver overheats. Use Value: LIMP output directly disables motor drivers and engages mechanical brakes during overtemperature - prevents unsafe motion without MCU execution. |
| Roof Module (Sunroof/Climate) | Trunk/Liftgate Actuator |
Use Scenario: Integrated sunroof, ambient lighting, and HVAC fan control via LIN network. IC Role / Device Role / Timing Role: UJA1079TW/5V0,118 serves as the power and communication hub, regulating MCU voltage, buffering LIN traffic, and detecting wake events from rain sensors or user switches. Use Value: Dual wake inputs (WAKE1/WAKE2) support simultaneous detection of rain sensor trigger and manual switch press - enables coordinated auto-close behavior. | Use Scenario: Power-operated liftgate with obstacle detection, soft-close, and anti-pinch logic. IC Role / Device Role / Timing Role: UJA1079TW/5V0,118 supplies 5 V to MCU and motor gate drivers, monitors V1 for cranking dips, and asserts LIMP on motor stall or thermal fault. Use Value: V1 undervoltage reset at 70 % threshold prevents erratic MCU behavior during engine start - ensures liftgate halts safely instead of reversing unpredictably. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LIN SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1076TW/5V0,118 | No integrated watchdog; lacks WDOFF pin and WD_and_Status register - reduces supervision capability but lowers BOM count where watchdog is handled externally. | Suitable for cost-sensitive LIN nodes where MCU-based watchdog suffices and thermal derating is not required. | Select UJA1076TW/5V0,118 only if watchdog functionality is implemented in software or external hardware - not a drop-in replacement for UJA1079TW/5V0,118. |
| TLE9471-2ES | Includes CAN FD + LIN dual interface; 5 V/300 mA regulator; integrated high-side switch; requires separate LIN transceiver - broader feature set but higher complexity and pin count. | Targeted at hybrid LIN/CAN domains (e.g., gateway modules) requiring both protocols and higher drive capability. | Choose TLE9471-2ES when CAN FD coexistence, higher current, or integrated switching is mandatory - not interchangeable due to different pinout and protocol stack. |
Compared with UJA1079TW/5V0,118, UJA1076TW/5V0,118 omits watchdog supervision entirely, while TLE9471-2ES adds CAN FD and high-side drive at the cost of larger footprint and non-LIN-native architecture - making UJA1079TW/5V0,118 the optimal choice for dedicated, watchdog-reliant LIN master ECUs with thermal constraints.
Availability
UJA1079TW/5V0,118 is available at Aetrix Electronics and suitable for automotive body electronics, seat control systems, and roof modules requiring stable component supply, long-term lifecycle support, and AEC-Q100–aligned reliability.
Supply support for UJA1079TW/5V0,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, and IoT applications, with deep expertise in automotive networking and power management ICs.
The UJA1079TW/5V0,118 belongs to NXP's System Basis Chip family, designed specifically to consolidate LIN ECU power, communication, and safety functions into a single AEC-Q100–qualified device for cost- and space-constrained automotive modules.
FAQ
What LIN protocol versions does the UJA1079TW/5V0,118 support?
The UJA1079TW/5V0,118 supports LIN 2.1 and SAE J2602 as primary standards, with full backward compatibility to LIN 2.0 and LIN 1.3. This ensures interoperability across legacy vehicle platforms and new designs without protocol translation or firmware adaptation. The transceiver also includes low-slope mode for optimized EMC in electrically noisy environments.
Does the UJA1079TW/5V0,118 include a watchdog timer?
Yes, the UJA1079TW/5V0,118 includes a programmable watchdog with Window, Timeout, and Off modes, clocked by an independent on-chip oscillator. The default period is 128 ms, adjustable via the NWP bits in the WD_and_Status register. Watchdog disable is possible via the WDOFF pin or software control in Standby mode - critical for fail-safe ECU supervision.
What is the purpose of the WBIAS pin on the UJA1079TW/5V0,118?
The WBIAS pin (Pin 28) provides controlled bias current to external wake-up switches, enabling low-power sampling of WAKE1 and WAKE2 inputs. It supports two sampling intervals - 16 ms or 64 ms - selectable via the WBC bit in the Mode_Control register. This reduces average wake pin current significantly versus continuous polling, extending battery life in always-on automotive modules.
Can the UJA1079TW/5V0,118 operate during engine cranking?
Yes, the UJA1079TW/5V0,118 operates down to 4.5 V on the BAT pin, complying with ISO 7637-4b (cranking pulse) and ISO 16750-2. Its V1 regulator maintains stable 5 V output under these conditions, and the V1 undervoltage reset can be configured to trigger at either 90 % or 70 % of nominal voltage - ensuring robust MCU operation or safe shutdown during low-VBAT events.
How does the LIMP output function in the UJA1079TW/5V0,118?
The LIMP output (Pin 17) is an active-LOW open-drain signal that activates automatically during overtemperature shutdown or when explicitly enabled via the LHC bit in the Mode_Control register. In Overtemp mode, UJA1079TW/5V0,118 drives LIMP LOW to engage hardware fallback mechanisms - such as disabling motor drivers or activating mechanical brakes - independent of MCU firmware execution.
UJA1079TW/5V0,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- SPI Serial
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1079TW/5V0,118 FAQ
1.How can I place an order for UJA1079TW/5V0,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1079TW/5V0,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of UJA1079TW/5V0,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1079TW/5V0,118 is usually 5 days.
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Once your UJA1079TW/5V0,118 order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for UJA1079TW/5V0,118?
For technical support, including UJA1079TW/5V0,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1079TW/5V0,118 requirements.
6.How does Aetrix verify that UJA1079TW/5V0,118 is sourced from the original manufacturer or authorized distributors?
All UJA1079TW/5V0,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1079TW/5V0,118 meets industry standards.
7.What is the process for return or replacement of UJA1079TW/5V0,118?
All UJA1079TW/5V0,118 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1079TW/5V0,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1079TW/5V0,118 part is unused and in its original packaging.
Return procedure for UJA1079TW/5V0,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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