NXP Semiconductors UJA1079TW/5V0/WD:1
- Part No.:
- UJA1079TW/5V0/WD:1
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Datasheet:
-
UJA1079TW/5V0/WD:1.pdf
- Description:
- IC INTFACE SPECIALIZED 32HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1079TW/5V0/WD:1 from NXP Semiconductors is a LIN 2.1–compliant System Basis Chip (SBC) integrating a 5 V/250 mA voltage regulator, advanced window/timeout watchdog, LIN transceiver with integrated termination diode, SPI interface, dual local wake-up inputs, and limp-home output - designed for automotive ECU power management and communication control in body electronics and sensor modules.
For engineers reviewing the UJA1079TW/5V0/WD:1 datasheet, UJA1079TW/5V0/WD:1 pinout, UJA1079TW/5V0/WD:1 application, or UJA1079TW/5V0/WD:1 equivalent, key selection criteria include LIN bus fault tolerance (±58 V), ISO 7637-3 transient protection, 5 V regulator accuracy (±2 % for master), HTSSOP32 thermal performance, and watchdog configurability via SPI register control.
Technical Context
The UJA1079TW/5V0/WD:1 implements a state-machine-based system controller managing Off/Standby/Normal/Sleep/Overtemp modes with deterministic transitions triggered by VBAT thresholds, wake events, or temperature. Its LIN transceiver supports low-slope mode (10.4 kbit/s) for EMC optimization and includes internal DLIN termination diode.
Power management integrates V1 regulation with external PNP transistor support (VEXCTRL/VEXCC pins), programmable undervoltage detection (90 % or 70 % of nominal), and bidirectional RSTN with selectable reset pulse width. The on-chip oscillator independently clocks the watchdog, decoupling timing from V1 stability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LIN Compliance | LIN 2.1, SAE J2602, backward-compatible with LIN 2.0 and LIN 1.3 - ensures interoperability across automotive LIN networks. |
| Voltage Regulator | 5 V ±2 % (master), ±3 % (slave); 250 mA max; supports external PNP transistor for thermal load sharing - powers MCU and peripherals reliably during cranking (VBAT ≥ 4.5 V). |
| Watchdog Modes | Window, Timeout, and Off modes; programmable period (8–4096 ms); independent on-chip oscillator clock - enables fail-safe timing supervision without MCU dependency. |
| ESD Protection | ±8 kV HBM on LIN/WAKE pins; ±6 kV IEC 61000-4-2 - meets automotive EMC requirements for harsh environments. |
| Bus Fault Tolerance | ±58 V short-circuit proof LIN pin; ISO 7637-3 transient protection on BAT/LIN - eliminates need for external TVS on LIN bus line. |
| SPI Interface | 16-bit full-duplex; register-mapped control (WD_and_Status, Mode_Control, Int_Control); read-only access option - enables real-time diagnostics and configuration without side effects. |
| Thermal Package | HTSSOP32 (SOT549-1); 6.1 mm × 11 mm; exposed die pad - provides low thermal resistance for sustained 250 mA operation in compact ECUs. |
Pinout & Package
Package: HTSSOP32 (SOT549-1), 6.1 mm × 11 mm body, 0.65 mm pitch, exposed die pad (thermally conductive, electrically isolated).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Regulated output | 5 V supply for MCU and peripherals; undervoltage warning/reset at 90 % or 70 % threshold. |
| LIN | LIN bus line | Differential bus interface with ±58 V fault tolerance and ISO 7637-3 transient immunity. |
| DLIN | LIN termination node | Connection point for internal termination diode - reduces external component count. |
| RSTN | Bidirectional reset | Drives LOW on system faults; accepts external reset; pulse width configurable via pull-up resistor. |
| WAKE1 / WAKE2 | Local wake inputs | Configurable sampling (16/64 ms); interrupt generation on edge; bias controlled via WBIAS pin. |
| LIMP | Limp-home output | Active-LOW fail-safe signal to activate degraded-mode hardware during critical failure. |
| SDI / SDO / SCK / SCSN | SPI interface | Full-duplex communication with microcontroller; register read/write access for diagnostics and control. |
| WDOFF | Watchdog disable | Hardware override: HIGH disables watchdog regardless of register settings - enables safe debug mode. |
Key Features
| Feature | Design Value |
|---|---|
| LIN transceiver integration | Eliminates discrete transceiver + termination + protection components; reduces BOM and PCB area by >40 % in typical LIN slave ECU. |
| Scalable 5 V regulator | Delivers stable 5 V ±2 % under cranking (VBAT = 4.5 V); external PNP support shifts >1 W dissipation off-die - extends thermal margin in sealed enclosures. |
| Advanced watchdog | Window mode detects both early and late MCU resets; timeout mode supports cyclic wake-up; independent oscillator prevents V1-related timing drift. |
| Multi-source wake capability | Simultaneous wake via LIN bus activity, WAKE1/WAKE2 inputs, or cyclic timer - enables ultra-low-power Standby mode (< 100 µA) with full responsiveness. |
| Fail-safe outputs | EN pin controls safety-critical hardware enable; LIMP pin asserts active-LOW during overtemperature or severe fault - meets ASIL-B functional safety intent. |
Applications
| Body Control Module (BCM) | Door Module |
|---|---|
Use Scenario: Centralized control of windows, locks, mirrors, and interior lighting in passenger vehicles. IC Role / Device Role / Timing Role: UJA1079TW/5V0/WD:1 acts as primary power manager and LIN interface hub - regulating MCU voltage, supervising startup, and relaying commands between CAN gateway and LIN slave nodes. Use Value: Integrated watchdog and limp-home output ensure fail-operational behavior during LIN bus faults or MCU lockup, maintaining basic door lock/unlock functionality. | Use Scenario: Distributed control unit inside vehicle door housing motor drivers, sensors, and switches. IC Role / Device Role / Timing Role: UJA1079TW/5V0/WD:1 supplies regulated 5 V to door MCU and LIN transceivers, detects local wake events (e.g., handle press), and triggers system wakeup with <100 µA standby current. Use Value: Dual wake inputs (WAKE1/WAKE2) and configurable sampling reduce false triggers from EMI while enabling fast response (< 100 ms) to mechanical actuation. |
| Roof Module | Seat Control Unit |
Use Scenario: Integration of sunroof, ambient lighting, and rain sensor in overhead console. IC Role / Device Role / Timing Role: UJA1079TW/5V0/WD:1 manages power sequencing, monitors LIN bus for sunroof position commands, and asserts LIMP output if MCU fails during glass movement. Use Value: ±58 V LIN bus tolerance prevents damage from accidental battery reverse connection or jump-start transients - critical in service-accessible roof locations. | Use Scenario: Motorized seat adjustment with position memory and heating control. IC Role / Device Role / Timing Role: UJA1079TW/5V0/WD:1 regulates 5 V for seat MCU and LIN transceivers, provides watchdog supervision for motor driver firmware, and signals limp-home mode if position sensor fails. Use Value: External PNP transistor support allows 500 mA total current delivery while keeping junction temperature below 125 °C - enabling continuous seat motor operation in hot climates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LIN SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1076TW/5V0/WD | No LIMP output; single wake input; no VEXCTRL/VEXCC pins for external PNP control - lower integration level. | Suitable for cost-sensitive LIN slaves without limp-home requirement or high-current loads. | Select UJA1076TW/5V0/WD only when limp-home functionality and external PNP support are unnecessary. |
| MC33816AEKR2 | Freescale/NXP part with 3.3 V regulator only; different SPI register map; no WDOFF pin - not pin-compatible. | Used in legacy 3.3 V MCU designs; requires redesign of regulator section and watchdog interface logic. | Choose MC33816AEKR2 only for migration from existing 3.3 V platforms where 5 V regulation is not required. |
Compared with UJA1076TW/5V0/WD, the UJA1079TW/5V0/WD:1 adds limp-home output and dual wake inputs for enhanced fail-safe capability; versus MC33816AEKR2, it delivers 5 V regulation and direct watchdog disable via WDOFF - simplifying safety-critical system design without MCU intervention.
Availability
UJA1079TW/5V0/WD:1 is available at Aetrix Electronics and suitable for automotive body electronics, door modules, roof consoles, and seat control units requiring stable component supply, long-term lifecycle support, and AEC-Q100 qualified reliability.
Supply support for UJA1079TW/5V0/WD:1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, and IoT applications, with deep expertise in automotive networking and power management ICs.
The UJA1079TW/5V0/WD:1 belongs to NXP's LIN System Basis Chip family, engineered specifically for automotive ECU consolidation - reducing discrete component count while delivering robust power, communication, and safety features in a single package.
FAQ
What LIN protocol versions does the UJA1079TW/5V0/WD:1 support?
The UJA1079TW/5V0/WD:1 supports LIN 2.1 and SAE J2602, and is backward-compatible with LIN 2.0 and LIN 1.3. It implements low-slope mode for optimized EMC performance and includes an integrated termination diode at the DLIN pin - eliminating external components required for legacy LIN transceivers.
How does the UJA1079TW/5V0/WD:1 handle undervoltage conditions on its 5 V regulator output?
The UJA1079TW/5V0/WD:1 monitors V1 output continuously and generates an undervoltage warning at 90 % of nominal voltage (4.5 V). It can be configured to assert a reset at either 90 % or 70 % (3.5 V) threshold via the RTHC bit in the Int_Control register - ensuring reliable MCU reset before brownout occurs.
Can the UJA1079TW/5V0/WD:1 drive higher current than 250 mA for the microcontroller supply?
Yes - the UJA1079TW/5V0/WD:1 supports external PNP transistor augmentation via VEXCTRL and VEXCC pins. With proper layout and heatsinking, total current delivery exceeds 500 mA while distributing thermal load across the PCB - confirmed in Section 2.1 and Figure 7 of the datasheet.
What is the function of the WDOFF pin on the UJA1079TW/5V0/WD:1?
The WDOFF pin on the UJA1079TW/5V0/WD:1 provides hardware-level watchdog disable: pulling it HIGH forces the watchdog into Off mode regardless of SPI register settings. This enables safe debug sessions and factory programming without risk of unintended resets - a feature explicitly documented in Sections 6.4 and Table 2.
Does the UJA1079TW/5V0/WD:1 meet automotive transient protection standards?
Yes - the UJA1079TW/5V0/WD:1 complies with ISO 7637-3 for battery and LIN bus transient immunity and provides ±58 V short-circuit protection on the LIN pin. Its ±8 kV HBM and ±6 kV IEC 61000-4-2 ESD ratings on LIN and wake pins exceed AEC-Q100 stress test requirements for under-hood and interior modules.
UJA1079TW/5V0/WD:1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-TSSOP (0.240", 6.10mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- SPI Serial
- Voltage - Supply:
- 4.5V ~ 28V
- Supplier Device Package:
- 32-HTSSOP
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1079TW/5V0/WD:1 FAQ
1.How can I place an order for UJA1079TW/5V0/WD:1 through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1079TW/5V0/WD:1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1079TW/5V0/WD:1 reliable?
The price and inventory of UJA1079TW/5V0/WD:1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1079TW/5V0/WD:1 is usually 5 days.
3.What payment methods are accepted for UJA1079TW/5V0/WD:1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1079TW/5V0/WD:1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1079TW/5V0/WD:1?
UJA1079TW/5V0/WD:1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1079TW/5V0/WD:1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1079TW/5V0/WD:1?
For technical support, including UJA1079TW/5V0/WD:1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1079TW/5V0/WD:1 requirements.
6.How does Aetrix verify that UJA1079TW/5V0/WD:1 is sourced from the original manufacturer or authorized distributors?
All UJA1079TW/5V0/WD:1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1079TW/5V0/WD:1 meets industry standards.
7.What is the process for return or replacement of UJA1079TW/5V0/WD:1?
All UJA1079TW/5V0/WD:1 units undergo pre-shipment inspection (PSI). If there is an issue with UJA1079TW/5V0/WD:1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1079TW/5V0/WD:1 part is unused and in its original packaging.
Return procedure for UJA1079TW/5V0/WD:1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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